From 0a4705dcfadb06b21b05b92cdd23a7cf61b27d85 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 16 Aug 2020 23:03:12 +0200 Subject: [PATCH] WIP: ARM: dts: add RK322x box device trees Signed-off-by: Alex Bee --- arch/arm/boot/dts/Makefile | 4 + arch/arm/boot/dts/rk3228a-box-h96mini.dts | 115 +++++++++ arch/arm/boot/dts/rk3228a-box.dts | 47 ++++ arch/arm/boot/dts/rk3228a-box.dtsi | 12 + arch/arm/boot/dts/rk3229-box-a95xr1.dts | 57 +++++ arch/arm/boot/dts/rk3229-box.dts | 50 ++++ arch/arm/boot/dts/rk3229-box.dtsi | 13 + arch/arm/boot/dts/rk3229-cpu-opp.dtsi | 50 ++++ arch/arm/boot/dts/rk322x-box-dcdc.dtsi | 163 +++++++++++++ arch/arm/boot/dts/rk322x-box.dtsi | 282 ++++++++++++++++++++++ 10 files changed, 793 insertions(+) create mode 100644 arch/arm/boot/dts/rk3228a-box-h96mini.dts create mode 100644 arch/arm/boot/dts/rk3228a-box.dts create mode 100644 arch/arm/boot/dts/rk3228a-box.dtsi create mode 100644 arch/arm/boot/dts/rk3229-box-a95xr1.dts create mode 100644 arch/arm/boot/dts/rk3229-box.dts create mode 100644 arch/arm/boot/dts/rk3229-box.dtsi create mode 100644 arch/arm/boot/dts/rk3229-cpu-opp.dtsi create mode 100644 arch/arm/boot/dts/rk322x-box-dcdc.dtsi create mode 100644 arch/arm/boot/dts/rk322x-box.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..4841972313e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -981,7 +981,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3188-bqedison2qc.dtb \ rk3188-px3-evb.dtb \ rk3188-radxarock.dtb \ + rk3228a-box.dtb \ + rk3228a-box-h96mini.dtb \ rk3228-evb.dtb \ + rk3229-box.dtb \ + rk3229-box-a95xr1.dtb \ rk3229-evb.dtb \ rk3229-xms6.dtb \ rk3288-evb-act8846.dtb \ diff --git a/arch/arm/boot/dts/rk3228a-box-h96mini.dts b/arch/arm/boot/dts/rk3228a-box-h96mini.dts new file mode 100644 index 000000000000..1041b6737d40 --- /dev/null +++ b/arch/arm/boot/dts/rk3228a-box-h96mini.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include "rk3228a-box.dtsi" + +/ { + compatible = "eledvb,h96mini", "rockchip,rk3228a-box", "rockchip,rk3229"; + model = "Rockchip RK3228A Box H96 mini"; + + leds { + compatible = "gpio-leds"; + + led_green { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + openvfd { + compatible = "open,vfd"; + dev_name = "openvfd"; + openvfd_gpio_clk = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + openvfd_gpio_dat = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + openvfd_display_type = <0x06000100>; + openvfd_dot_bits = [00 01 03 02 04 05 06]; + }; + +}; + +&emmc { + mmc-hs200-1_8v; + status = "okay"; +}; + +&gmac { + tx_delay = <0x26>; + rx_delay = <0x11>; +}; + +&ir_receiver { + status = "okay"; +}; + +&pinctrl { + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bt { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&power_key { + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + disable-wp; + status = "okay"; +}; + +&uart1 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + host-wakeup-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + }; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3228a-box.dts b/arch/arm/boot/dts/rk3228a-box.dts new file mode 100644 index 000000000000..e68ef44b95c9 --- /dev/null +++ b/arch/arm/boot/dts/rk3228a-box.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3228a-box.dtsi" + +/ { + model = "Rockchip RK3228A Box"; + + leds { + compatible = "gpio-leds"; + + led_blue { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + +}; + +&emmc { + status = "okay"; +}; + +&ir_receiver { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3228a-box.dtsi b/arch/arm/boot/dts/rk3228a-box.dtsi new file mode 100644 index 000000000000..056945c6c9a7 --- /dev/null +++ b/arch/arm/boot/dts/rk3228a-box.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk322x-box-dcdc.dtsi" + +/ { + + model = "Rockchip RK3228A Box"; + compatible = "rockchip,rk3228a-box", "rockchip,rk3229"; + +}; diff --git a/arch/arm/boot/dts/rk3229-box-a95xr1.dts b/arch/arm/boot/dts/rk3229-box-a95xr1.dts new file mode 100644 index 000000000000..b3695fb0b255 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-box-a95xr1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include "rk3229-box.dtsi" + +/ { + model = "Rockchip RK3229 Box A95X-R1"; + + leds { + compatible = "gpio-leds"; + + led_blue { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "rc-feedback"; + }; + }; + +}; + +&emmc { + mmc-hs200-1_8v; + status = "okay"; +}; + +&gmac { + tx_delay = <0x26>; + rx_delay = <0x11>; +}; + +&ir_receiver { + status = "okay"; +}; + +&power_key { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + disable-wp; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3229-box.dts b/arch/arm/boot/dts/rk3229-box.dts new file mode 100644 index 000000000000..b63e61cda257 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-box.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3229-box.dtsi" + +/ { + model = "Rockchip RK3229 Box"; + + leds { + compatible = "gpio-leds"; + + led_green { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_red { + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&emmc { + status = "okay"; +}; + +&ir_receiver { + status = "okay"; +}; + +&power_key { + status = "okay"; +}; + +&sdio { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/rk3229-box.dtsi b/arch/arm/boot/dts/rk3229-box.dtsi new file mode 100644 index 000000000000..4499b85351e0 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-box.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk322x-box-dcdc.dtsi" +#include "rk3229-cpu-opp.dtsi" + +/ { + + model = "Rockchip RK3229 Box"; + compatible = "rockchip,rk3229-box", "rockchip,rk3229"; + +}; diff --git a/arch/arm/boot/dts/rk3229-cpu-opp.dtsi b/arch/arm/boot/dts/rk3229-cpu-opp.dtsi new file mode 100644 index 000000000000..c1c7613bab11 --- /dev/null +++ b/arch/arm/boot/dts/rk3229-cpu-opp.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + compatible = "rockchip,rk3229"; + + /delete-node/ opp-table0; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1400000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000 975000 1400000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000 1000000 1400000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000 1175000 1400000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000 1275000 1400000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1325000 1325000 1400000>; + }; + opp-1392000000 { + opp-hz = /bits/ 64 <1392000000>; + opp-microvolt = <1350000 1350000 1400000>; + }; + opp-1464000000 { + opp-hz = /bits/ 64 <1464000000>; + opp-microvolt = <1400000 1400000 1400000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk322x-box-dcdc.dtsi b/arch/arm/boot/dts/rk322x-box-dcdc.dtsi new file mode 100644 index 000000000000..34273f3ff9ae --- /dev/null +++ b/arch/arm/boot/dts/rk322x-box-dcdc.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk322x-box.dtsi" + +/ { + + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + + vcc_otg: vcc-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vccio_1v8>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_arm: vdd-arm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 2000 0>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <4000>; + pwm-dutycycle-range = <90 0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 0>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <4000>; + pwm-dutycycle-range = <100 0>; + regulator-always-on; + regulator-boot-on; + }; + +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&io_domains { + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio4-supply = <&vccio_3v3>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; +}; + +&gpu { + mali-supply = <&vdd_log>; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pin_pull_down>; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_pin_pull_up>; + status = "okay"; +}; + +&u2phy0 { + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + }; + + u2phy0_otg: otg-port { + phy-supply = <&vcc_otg>; + }; +}; + +&u2phy1 { + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + }; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_otg>; + }; +}; diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi new file mode 100644 index 000000000000..ef5fa28d8ee9 --- /dev/null +++ b/arch/arm/boot/dts/rk322x-box.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk322x.dtsi" + +/ { + model = "Rockchip RK322x Box"; + compatible = "rockchip,rk3229"; + + chosen { + bootargs = "earlyprintk=uart8250,mmio32,0x11030000"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power_key: power-key { + label = "GPIO Key Power"; + gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + status = "disabled"; + }; + }; + + ir_receiver: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + status = "disabled"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; + }; + + timer { + /delete-property/ arm,cpu-registers-not-fw-configured; + }; +}; + +&cpu_alert1 { + temperature = <105000>; +}; + +&cpu_crit { + temperature = <115000>; +}; + +&cpu_thermal { + cooling-maps { + /delete-node/ map0; + }; +}; + +&cru { + assigned-clocks = <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_VOP>; + + assigned-clock-rates = <1200000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>, <400000000>; +}; + +&emmc { + cap-mmc-highspeed; + keep-power-in-suspend; + non-removable; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-handle = <&phy>; + phy-mode = "rmii"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&cru SCLK_MAC_PHY>; + phy-is-integrated; + resets = <&cru SRST_MACPHY>; + }; + }; +}; + +&gpu { + assigned-clocks = <&cru ACLK_GPU>; + assigned-clock-rates = <300000000>; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdmi_phy { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&pinctrl { + + ir { + ir_int: ir-int { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pwm1 { + pwm1_pin_pull_down: pwm1-pin-pull-down { + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>; + }; + }; + + pwm2 { + pwm2_pin_pull_up: pwm2-pin-pull-up { + rockchip,pins = <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&sdio { + mmc-pwrseq = <&sdio_pwrseq>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + no-sd; +}; + +&sdmmc { + cap-sd-highspeed; + keep-power-in-suspend; + no-sdio; +}; + +&tsadc { + rockchip,grf = <&grf>; + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <120000>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP>; + assigned-clock-parents = <&cru SCLK_HDMI_PHY>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +};