diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index f1fed12c4..36ff5827d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -41,6 +41,12 @@
 #include "pinconf.h"
 #include "pinctrl-rockchip.h"
 
+#define RK3308_SOC_CON0			0x300
+#define RK3308_SOC_CON0_DOMAINS ((BIT(9)-1)-BIT(7))
+#define RK3308_SOC_CON0_DEFAULT 0x10  //default if no io_1v8_domains specified
+//note that this is supposed to be the reset value, but something early
+//in boot sets SOC_CON0 to zero
+
 /*
  * Generate a bitmask for setting a value (v) with a write mask bit in hiword
  * register 31:16 area.
@@ -3177,6 +3183,24 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	if (ctrl->type == RK3308) {
+	/*
+	 * Update GRF_SOC_CON0 early to reflect board's (fixed) I/O domain voltages
+	 * The io-1v8-domains property may be specified to override default value
+	 */
+		u32 ioVoltSelect = RK3308_SOC_CON0_DEFAULT;
+		device_property_read_u32(dev, "io-1v8-domains", &ioVoltSelect);
+		if (ioVoltSelect & ~RK3308_SOC_CON0_DOMAINS) {
+			dev_warn(dev, "ignored invalid io-1v8-domains\n");
+			ioVoltSelect = RK3308_SOC_CON0_DEFAULT;
+		}
+	  ret = regmap_write(info->regmap_base, RK3308_SOC_CON0,
+		ioVoltSelect | (RK3308_SOC_CON0_DOMAINS << 16));
+		dev_info(dev, "1.8V I/O domains assigned 0x%03x\n", ioVoltSelect);
+		if (ret < 0)
+			dev_warn(dev, "Couldn't update 1.8V I/O domains\n");
+	}
+
 	platform_set_drvdata(pdev, info);
 
 	ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c
index 83f5354ba..9df513d12 100644
--- a/drivers/soc/rockchip/io-domain.c
+++ b/drivers/soc/rockchip/io-domain.c
@@ -39,10 +39,6 @@
 #define RK3288_SOC_CON2_FLASH0		BIT(7)
 #define RK3288_SOC_FLASH_SUPPLY_NUM	2
 
-#define RK3308_SOC_CON0			0x300
-#define RK3308_SOC_CON0_VCCIO3		BIT(8)
-#define RK3308_SOC_VCCIO3_SUPPLY_NUM	3
-
 #define RK3328_SOC_CON4			0x410
 #define RK3328_SOC_CON4_VCCIO2		BIT(7)
 #define RK3328_SOC_VCCIO2_SUPPLY_NUM	1
@@ -233,30 +229,6 @@ static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
 		dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
 }
 
-static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
-{
-	int ret;
-	u32 val;
-
-	/* if no vccio3 supply we should leave things alone */
-	if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
-		return;
-
-	/*
-	 * vccio3 iodomain voltage should be determined by GPIO4 input state
-	 * RockPI-S uses this to drive the SDIO interface at 50Mhz
-	 * (otherwise SDIO clock will be limited to 10Mhz)
-	 *
-	 * Note that setting vccio4 [rather than vccio3] is observed to reduce
-	 * the rise time of SDIO-clk from 30ns to 5ns.
-	 * The CON0_VCCIO3 control bit appears to influence vccio4.
-	 */
-	val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
-	ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
-	if (ret < 0)
-		dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
-}
-
 static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
 {
 	int ret;
@@ -404,19 +376,6 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
 	.init = rk3288_iodomain_init,
 };
 
-static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
-	.grf_offset = 0x300,
-	.supply_names = {
-		"vccio0",
-		"vccio1",
-		"vccio2",
-		"vccio3",
-		"vccio4",
-		"vccio5",
-	},
-	.init = rk3308_iodomain_init,
-};
-
 static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
 	.grf_offset = 0x410,
 	.supply_names = {
@@ -553,10 +512,6 @@ static const struct of_device_id rockchip_iodomain_match[] = {
 		.compatible = "rockchip,rk3288-io-voltage-domain",
 		.data = &soc_data_rk3288
 	},
-	{
-		.compatible = "rockchip,rk3308-io-voltage-domain",
-		.data = &soc_data_rk3308
-	},
 	{
 		.compatible = "rockchip,rk3328-io-voltage-domain",
 		.data = &soc_data_rk3328
