From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 9 Jul 2022 23:55:01 +0200 Subject: dt-bindings: clock: Add StarFive JH7110 system clock definitions Add all clock outputs for the StarFive JH7110 system clock generator. Signed-off-by: Emil Renner Berthing --- include/dt-bindings/clock/starfive-jh7110-sys.h | 215 ++++++++++ 1 file changed, 215 insertions(+) diff --git a/include/dt-bindings/clock/starfive-jh7110-sys.h b/include/dt-bindings/clock/starfive-jh7110-sys.h new file mode 100755 index 000000000000..5ef643895a7a --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7110-sys.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2022 Emil Renner Berthing + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__ + +#define JH7110_SYSCLK_CPU_ROOT 0 /* clk_cpu_root */ +#define JH7110_SYSCLK_CPU_CORE 1 /* clk_cpu_core */ +#define JH7110_SYSCLK_CPU_BUS 2 /* clk_cpu_bus */ +#define JH7110_SYSCLK_GPU_ROOT 3 /* clk_gpu_root */ +#define JH7110_SYSCLK_PERH_ROOT 4 /* clk_perh_root */ +#define JH7110_SYSCLK_BUS_ROOT 5 /* clk_bus_root */ +#define JH7110_SYSCLK_NOCSTG_BUS 6 /* clk_nocstg_bus */ +#define JH7110_SYSCLK_AXI_CFG0 7 /* clk_axi_cfg0 */ +#define JH7110_SYSCLK_STG_AXIAHB 8 /* clk_stg_axiahb */ +#define JH7110_SYSCLK_AHB0 9 /* clk_ahb0 */ +#define JH7110_SYSCLK_AHB1 10 /* clk_ahb1 */ +#define JH7110_SYSCLK_APB_BUS_FUNC 11 /* clk_apb_bus_func */ +#define JH7110_SYSCLK_APB0 12 /* clk_apb0 */ +#define JH7110_SYSCLK_PLL0_DIV2 13 /* clk_pll0_div2 */ +#define JH7110_SYSCLK_PLL1_DIV2 14 /* clk_pll1_div2 */ +#define JH7110_SYSCLK_PLL2_DIV2 15 /* clk_pll2_div2 */ +#define JH7110_SYSCLK_AUDIO_ROOT 16 /* clk_audio_root */ +#define JH7110_SYSCLK_MCLK_INNER 17 /* clk_mclk_inner */ +#define JH7110_SYSCLK_MCLK 18 /* clk_mclk */ +#define JH7110_SYSCLK_MCLK_OUT 19 /* clk_mclk_out */ +#define JH7110_SYSCLK_ISP_2X 20 /* clk_isp_2x */ +#define JH7110_SYSCLK_ISP_AXI 21 /* clk_isp_axi */ +#define JH7110_SYSCLK_GCLK0 22 /* clk_gclk0 */ +#define JH7110_SYSCLK_GCLK1 23 /* clk_gclk1 */ +#define JH7110_SYSCLK_GCLK2 24 /* clk_gclk2 */ +#define JH7110_SYSCLK_CORE 25 /* clk_u0_u7mc_sft7110_core_clk */ +#define JH7110_SYSCLK_CORE1 26 /* clk_u0_u7mc_sft7110_core_clk1 */ +#define JH7110_SYSCLK_CORE2 27 /* clk_u0_u7mc_sft7110_core_clk2 */ +#define JH7110_SYSCLK_CORE3 28 /* clk_u0_u7mc_sft7110_core_clk3 */ +#define JH7110_SYSCLK_CORE4 29 /* clk_u0_u7mc_sft7110_core_clk4 */ +#define JH7110_SYSCLK_DEBUG 30 /* clk_u0_u7mc_sft7110_debug_clk */ +#define JH7110_SYSCLK_RTC_TOGGLE 31 /* clk_u0_u7mc_sft7110_rtc_toggle */ +#define JH7110_SYSCLK_TRACE0 32 /* clk_u0_u7mc_sft7110_trace_clk0 */ +#define JH7110_SYSCLK_TRACE1 33 /* clk_u0_u7mc_sft7110_trace_clk1 */ +#define JH7110_SYSCLK_TRACE2 34 /* clk_u0_u7mc_sft7110_trace_clk2 */ +#define JH7110_SYSCLK_TRACE3 35 /* clk_u0_u7mc_sft7110_trace_clk3 */ +#define JH7110_SYSCLK_TRACE4 36 /* clk_u0_u7mc_sft7110_trace_clk4 */ +#define JH7110_SYSCLK_TRACE_COM 37 /* clk_u0_u7mc_sft7110_trace_com_clk */ +#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 /* clk_u0_u7mc_sft7110_noc_bus_clk_cpu_axi */ +#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 /* clk_u0_u7mc_sft7110_noc_bus_clk_axicfg0_axi */ +#define JH7110_SYSCLK_OSC_DIV2 40 /* clk_osc_div2 */ +#define JH7110_SYSCLK_PLL1_DIV4 41 /* clk_pll1_div4 */ +#define JH7110_SYSCLK_PLL1_DIV8 42 /* clk_pll1_div8 */ +#define JH7110_SYSCLK_DDR_BUS 43 /* clk_ddr_bus */ +#define JH7110_SYSCLK_DDR_AXI 44 /* clk_u0_ddr_sft7110_clk_axi */ +#define JH7110_SYSCLK_GPU_CORE 45 /* clk_gpu_core */ +#define JH7110_SYSCLK_GPU_CORE_CLK 46 /* clk_u0_img_gpu_core_clk */ +#define JH7110_SYSCLK_GPU_SYS_CLK 47 /* clk_u0_img_gpu_sys_clk */ +#define JH7110_SYSCLK_GPU_APB 48 /* clk_u0_img_gpu_clk_apb */ +#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 /* clk_u0_img_gpu_rtc_toggle */ +#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 /* clk_u0_sft7110_noc_bus_clk_gpu_axi */ +#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 /* clk_u0_dom_isp_top_clk_ispcore_2x */ +#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 /* clk_u0_dom_isp_top_clk_isp_axi */ +#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 /* clk_u0_sft7110_noc_bus_clk_isp_axi */ +#define JH7110_SYSCLK_HIFI4_CORE 54 /* clk_hifi4_core */ +#define JH7110_SYSCLK_HIFI4_AXI 55 /* clk_hifi4_axi */ +#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 /* clk_u0_axi_cfg1_dec_clk_main */ +#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 /* clk_u0_axi_cfg1_dec_clk_ahb */ +#define JH7110_SYSCLK_VOUT_SRC 58 /* clk_u0_dom_vout_top_vout_src */ +#define JH7110_SYSCLK_VOUT_AXI 59 /* clk_vout_axi */ +#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 /* clk_u0_sft7110_noc_bus_clk_disp_axi */ +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 /* clk_u0_dom_vout_top_clk_vout_ahb */ +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 /* clk_u0_dom_vout_top_clk_vout_axi */ +#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 /* clk_u0_dom_vout_top_clk_hdmitx0_mclk */ +#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 /* clk_u0_dom_vout_top_clk_mipiphy_ref */ +#define JH7110_SYSCLK_JPEGC_AXI 65 /* clk_jpegc_axi */ +#define JH7110_SYSCLK_CODAJ12_AXI 66 /* clk_CODAJ12_clk_axi */ +#define JH7110_SYSCLK_CODAJ12_CORE 67 /* clk_CODAJ12_clk_core */ +#define JH7110_SYSCLK_CODAJ12_APB 68 /* clk_CODAJ12_clk_apb */ +#define JH7110_SYSCLK_VDEC_AXI 69 /* clk_vdec_axi */ +#define JH7110_SYSCLK_WAVE511_AXI 70 /* clk_u0_WAVE511_clk_axi */ +#define JH7110_SYSCLK_WAVE511_BPU 71 /* clk_u0_WAVE511_clk_bpu */ +#define JH7110_SYSCLK_WAVE511_VCE 72 /* clk_u0_WAVE511_clk_vce */ +#define JH7110_SYSCLK_WAVE511_APB 73 /* clk_u0_WAVE511_clk_apb */ +#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 /* clk_u0_vdec_jpg_arb_jpgclk */ +#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 /* clk_u0_vdec_jpg_arb_mainclk */ +#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 /* clk_u0_sft7110_noc_bus_clk_vdec_axi */ +#define JH7110_SYSCLK_VENC_AXI 77 /* clk_vec_axi */ +#define JH7110_SYSCLK_WAVE420L_AXI 78 /* clk_u0_wave420l_clk_axi */ +#define JH7110_SYSCLK_WAVE420L_BPU 79 /* clk_u0_wave420l_clk_bpu */ +#define JH7110_SYSCLK_WAVE420L_VCE 80 /* clk_u0_wave420l_clk_vce */ +#define JH7110_SYSCLK_WAVE420L_APB 81 /* clk_u0_wave420l_clk_apb */ +#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 /* clk_u0_sft7110_noc_bus_clk_venc_axi */ +#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 /* clk_u0_axi_cfg0_dec_clk_main_div */ +#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 /* clk_u0_axi_cfg0_dec_clk_main */ +#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 /* clk_u0_axi_cfg0_dec_clk_hifi4 */ +#define JH7110_SYSCLK_AXIMEM2_AXI 86 /* clk_u2_aximem_128b_clk_axi */ +#define JH7110_SYSCLK_QSPI_AHB 87 /* clk_u0_cdns_qspi_clk_ahb */ +#define JH7110_SYSCLK_QSPI_APB 88 /* clk_u0_cdns_qspi_clk_apb */ +#define JH7110_SYSCLK_QSPI_REF_SRC 89 /* clk_u0_cdns_qspi_ref_src */ +#define JH7110_SYSCLK_QSPI_REF 90 /* clk_u0_cdns_qspi_clk_ref */ +#define JH7110_SYSCLK_SDIO0_AHB 91 /* clk_u0_dw_sdio_clk_ahb */ +#define JH7110_SYSCLK_SDIO1_AHB 92 /* clk_u1_dw_sdio_clk_ahb */ +#define JH7110_SYSCLK_SDIO0_SDCARD 93 /* clk_u0_dw_sdio_clk_sdcard */ +#define JH7110_SYSCLK_SDIO1_SDCARD 94 /* clk_u1_dw_sdio_clk_sdcard */ +#define JH7110_SYSCLK_USB_125M 95 /* clk_usb_125m */ +#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 /* clk_u0_sft7110_noc_bus_clk_stg_axi */ +#define JH7110_SYSCLK_GMAC1_AHB 97 /* clk_u1_dw_gmac5_axi64_clk_ahb */ +#define JH7110_SYSCLK_GMAC1_AXI 98 /* clk_u1_dw_gmac5_axi64_clk_axi */ +#define JH7110_SYSCLK_GMAC_SRC 99 /* clk_gmac_src */ +#define JH7110_SYSCLK_GMAC1_GTXCLK 100 /* clk_gmac1_gtxclk */ +#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 /* clk_gmac1_rmii_rtx */ +#define JH7110_SYSCLK_GMAC1_PTP 102 /* clk_u1_dw_gmac5_axi64_clk_ptp */ +#define JH7110_SYSCLK_GMAC1_RX 103 /* clk_u1_dw_gmac5_axi64_clk_rx */ +#define JH7110_SYSCLK_GMAC1_RX_INV 104 /* clk_u1_dw_gmac5_axi64_clk_rx_inv */ +#define JH7110_SYSCLK_GMAC1_TX 105 /* clk_u1_dw_gmac5_axi64_clk_tx */ +#define JH7110_SYSCLK_GMAC1_TX_INV 106 /* clk_u1_dw_gmac5_axi64_clk_tx_inv */ +#define JH7110_SYSCLK_GMAC1_GTXC 107 /* clk_gmac1_gtxc */ +#define JH7110_SYSCLK_GMAC0_GTXCLK 108 /* clk_gmac0_gtxclk */ +#define JH7110_SYSCLK_GMAC0_PTP 109 /* clk_gmac0_ptp */ +#define JH7110_SYSCLK_GMAC_PHY 110 /* clk_gmac_phy */ +#define JH7110_SYSCLK_GMAC0_GTXC 111 /* clk_gmac0_gtxc */ +#define JH7110_SYSCLK_IOMUX 112 /* clk_u0_sys_iomux_pclk */ +#define JH7110_SYSCLK_MAILBOX 113 /* clk_u0_mailbox_clk_apb */ +#define JH7110_SYSCLK_INT_CTRL_APB 114 /* clk_int_ctrl_clk_apb */ +#define JH7110_SYSCLK_CAN0_APB 115 /* clk_u0_can_ctrl_clk_apb */ +#define JH7110_SYSCLK_CAN0_TIMER 116 /* clk_u0_can_ctrl_clk_timer */ +#define JH7110_SYSCLK_CAN0_CAN 117 /* clk_u0_can_ctrl_clk_can */ +#define JH7110_SYSCLK_CAN1_APB 118 /* clk_u1_can_ctrl_clk_apb */ +#define JH7110_SYSCLK_CAN1_TIMER 119 /* clk_u1_can_ctrl_clk_timer */ +#define JH7110_SYSCLK_CAN1_CAN 120 /* clk_u1_can_ctrl_clk_can */ +#define JH7110_SYSCLK_PWM_APB 121 /* clk_u0_pwm_8ch_clk_apb */ +#define JH7110_SYSCLK_WDT_APB 122 /* clk_u0_dskit_wdt_clk_apb */ +#define JH7110_SYSCLK_WDT_CORE 123 /* clk_u0_dskit_wdt_clk_wdt */ +#define JH7110_SYSCLK_TIMER_APB 124 /* clk_u0_si5_timer_clk_apb */ +#define JH7110_SYSCLK_TIMER0 125 /* clk_u0_si5_timer_clk_timer0 */ +#define JH7110_SYSCLK_TIMER1 126 /* clk_u0_si5_timer_clk_timer1 */ +#define JH7110_SYSCLK_TIMER2 127 /* clk_u0_si5_timer_clk_timer2 */ +#define JH7110_SYSCLK_TIMER3 128 /* clk_u0_si5_timer_clk_timer3 */ +#define JH7110_SYSCLK_TEMP_APB 129 /* clk_u0_temp_sensor_clk_apb */ +#define JH7110_SYSCLK_TEMP_CORE 130 /* clk_u0_temp_sensor_clk_temp */ +#define JH7110_SYSCLK_SPI0_APB 131 /* clk_u0_ssp_spi_clk_apb */ +#define JH7110_SYSCLK_SPI1_APB 132 /* clk_u1_ssp_spi_clk_apb */ +#define JH7110_SYSCLK_SPI2_APB 133 /* clk_u2_ssp_spi_clk_apb */ +#define JH7110_SYSCLK_SPI3_APB 134 /* clk_u3_ssp_spi_clk_apb */ +#define JH7110_SYSCLK_SPI4_APB 135 /* clk_u4_ssp_spi_clk_apb */ +#define JH7110_SYSCLK_SPI5_APB 136 /* clk_u5_ssp_spi_clk_apb */ +#define JH7110_SYSCLK_SPI6_APB 137 /* clk_u6_ssp_spi_clk_apb */ +#define JH7110_SYSCLK_I2C0_APB 138 /* clk_u0_dw_i2c_clk_apb */ +#define JH7110_SYSCLK_I2C1_APB 139 /* clk_u1_dw_i2c_clk_apb */ +#define JH7110_SYSCLK_I2C2_APB 140 /* clk_u2_dw_i2c_clk_apb */ +#define JH7110_SYSCLK_I2C3_APB 141 /* clk_u3_dw_i2c_clk_apb */ +#define JH7110_SYSCLK_I2C4_APB 142 /* clk_u4_dw_i2c_clk_apb */ +#define JH7110_SYSCLK_I2C5_APB 143 /* clk_u5_dw_i2c_clk_apb */ +#define JH7110_SYSCLK_I2C6_APB 144 /* clk_u6_dw_i2c_clk_apb */ +#define JH7110_SYSCLK_UART0_APB 145 /* clk_u0_dw_uart_clk_apb */ +#define JH7110_SYSCLK_UART0_CORE 146 /* clk_u0_dw_uart_clk_core */ +#define JH7110_SYSCLK_UART1_APB 147 /* clk_u1_dw_uart_clk_apb */ +#define JH7110_SYSCLK_UART1_CORE 148 /* clk_u1_dw_uart_clk_core */ +#define JH7110_SYSCLK_UART2_APB 149 /* clk_u2_dw_uart_clk_apb */ +#define JH7110_SYSCLK_UART2_CORE 150 /* clk_u2_dw_uart_clk_core */ +#define JH7110_SYSCLK_UART3_APB 151 /* clk_u3_dw_uart_clk_apb */ +#define JH7110_SYSCLK_UART3_CORE 152 /* clk_u3_dw_uart_clk_core */ +#define JH7110_SYSCLK_UART4_APB 153 /* clk_u4_dw_uart_clk_apb */ +#define JH7110_SYSCLK_UART4_CORE 154 /* clk_u4_dw_uart_clk_core */ +#define JH7110_SYSCLK_UART5_APB 155 /* clk_u5_dw_uart_clk_apb */ +#define JH7110_SYSCLK_UART5_CORE 156 /* clk_u5_dw_uart_clk_core */ +#define JH7110_SYSCLK_PWMDAC_APB 157 /* clk_u0_pwmdac_clk_apb */ +#define JH7110_SYSCLK_PWMDAC_CORE 158 /* clk_u0_pwmdac_clk_core */ +#define JH7110_SYSCLK_SPDIF_APB 159 /* clk_u0_cdns_spdif_clk_apb */ +#define JH7110_SYSCLK_SPDIF_CORE 160 /* clk_u0_cdns_spdif_clk_core */ +#define JH7110_SYSCLK_I2STX0_APB 161 /* clk_u0_i2stx_4ch_clk_apb */ +#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 /* clk_i2stx_4ch0_bclk_mst */ +#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 /* clk_i2stx_4ch0_bclk_mst_inv */ +#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 /* clk_i2stx_4ch0_lrck_mst */ +#define JH7110_SYSCLK_I2STX0_BCLK 165 /* clk_u0_i2stx_4ch_bclk */ +#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 /* clk_u0_i2stx_4ch_bclk_n */ +#define JH7110_SYSCLK_I2STX0_LRCK 167 /* clk_u0_i2stx_4ch_lrck */ +#define JH7110_SYSCLK_I2STX1_APB 168 /* clk_u1_i2stx_4ch_clk_apb */ +#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 /* clk_i2stx_4ch1_bclk_mst */ +#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 /* clk_i2stx_4ch1_bclk_mst_inv */ +#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 /* clk_i2stx_4ch1_lrck_mst */ +#define JH7110_SYSCLK_I2STX1_BCLK 172 /* clk_u1_i2stx_4ch_bclk */ +#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 /* clk_u1_i2stx_4ch_bclk_n */ +#define JH7110_SYSCLK_I2STX1_LRCK 174 /* clk_u1_i2stx_4ch_lrck */ +#define JH7110_SYSCLK_I2SRX_APB 175 /* clk_u0_i2srx_3ch_clk_apb */ +#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 /* clk_i2srx_3ch_bclk_mst */ +#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 /* clk_i2srx_3ch_bclk_mst_inv */ +#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 /* clk_i2srx_3ch_lrck_mst */ +#define JH7110_SYSCLK_I2SRX_BCLK 179 /* clk_u0_i2srx_3ch_bclk */ +#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 /* clk_u0_i2srx_3ch_bclk_n */ +#define JH7110_SYSCLK_I2SRX_LRCK 181 /* clk_u0_i2srx_3ch_lrck */ +#define JH7110_SYSCLK_PDM_DMIC 182 /* clk_u0_pdm_4mic_clk_dmic */ +#define JH7110_SYSCLK_PDM_APB 183 /* clk_u0_pdm_4mic_clk_apb */ +#define JH7110_SYSCLK_TDM_AHB 184 /* clk_u0_tdm16slot_clk_ahb */ +#define JH7110_SYSCLK_TDM_APB 185 /* clk_u0_tdm16slot_clk_apb */ +#define JH7110_SYSCLK_TDM_INTERNAL 186 /* clk_tdm_internal */ +#define JH7110_SYSCLK_TDM_CLK_TDM 187 /* clk_u0_tdm16slot_clk_tdm */ +#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 /* clk_u0_tdm16slot_clk_tdm_n */ +#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 /* clk_u0_jtag_certification_trng_clk */ + +#define JH7110_SYSCLK_PLL0_OUT 190 +#define JH7110_SYSCLK_PLL1_OUT 191 +#define JH7110_SYSCLK_PLL2_OUT 192 +#define JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK 193 +#define JH7110_SYSCLK_U2_PCLK_MUX_PCLK 194 +#define JH7110_SYSCLK_APB_BUS 195 +#define JH7110_SYSCLK_AXI_CFG1 196 +#define JH7110_SYSCLK_APB12 197 +#define JH7110_SYSCLK_VOUT_ROOT 198 +#define JH7110_SYSCLK_VENC_ROOT 199 +#define JH7110_SYSCLK_VDEC_ROOT 200 +#define JH7110_SYSCLK_GMACUSB_ROOT 201 + +#define JH7110_SYSCLK_END 202 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_SYS_H__ */ -- Armbian