From f19ce7bb7d72e3637d9b10b6289404fde3d85ced Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 24 Oct 2022 03:20:27 +0200 Subject: [PATCH 295/389] arm64: dts: rk3399-pinephone-pro: Use unused GPLL for VOPs DCLK GPLL allows us to get 74.25MHz just by dividing 594 by 8. Use GPLL by default for VOPs. Signed-off-by: Ondrej Jirman --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 05e2276ac1a2..0b59c2e7965d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -1540,7 +1540,7 @@ &vopb { status = "okay"; assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; - assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP0_FRAC>; + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>; }; &vopb_mmu { @@ -1551,7 +1551,7 @@ &vopl { status = "okay"; assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; - assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP1_FRAC>; + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>; }; &vopl_mmu { -- 2.35.3