From f16003a3392cc3e767e4c6e145f48f5964cf0942 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Thu, 29 Feb 2024 23:26:32 +0400 Subject: [PATCH 1/3] arm64: dts: rockchip: enable built-in thermal monitoring on RK3588 Include thermal zones information in device tree for RK3588 variants. This also enables the TSADC controller unconditionally on all boards to ensure that thermal protections are in place via throttling and emergency reset, once OPPs are added to enable CPU DVFS. The default settings (using CRU as the emergency reset mechanism) should work on all boards regardless of their wiring, as CRU resets do not depend on any external components. Boards that have the TSHUT signal wired to the reset line of the PMIC may opt to switch to GPIO tshut mode instead (rockchip,hw-tshut-mode = <1>;) It seems though that downstream kernels don't use that, even for those boards where the wiring allows for GPIO based tshut, such as Radxa Rock 5B [1], [2], [3] [1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts#L540 [2] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi#L5433 [3] https://dl.radxa.com/rock5/5b/docs/hw/radxa_rock_5b_v1423_sch.pdf page 11 (TSADC_SHUT_H) Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240229-rk-dts-additions-v3-1-6afe8473a631@gmail.com Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 176 +++++++++++++++++++++- 1 file changed, 175 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 87b83c87bd55..56fafb09bcbb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3588"; @@ -2229,7 +2230,180 @@ tsadc: tsadc@fec00000 { pinctrl-1 = <&tsadc_shut>; pinctrl-names = "gpio", "otpout"; #thermal-sensor-cells = <1>; - status = "disabled"; + status = "okay"; + }; + + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + /* threshold to start collecting temperature + * statistics e.g. with the IPA governor + */ + bigcore0_alert0: bigcore0-alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + /* actual control temperature */ + bigcore0_alert1: bigcore0-alert1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore0_crit: bigcore0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&bigcore0_alert1>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + /* threshold to start collecting temperature + * statistics e.g. with the IPA governor + */ + bigcore2_alert0: bigcore2-alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + /* actual control temperature */ + bigcore2_alert1: bigcore2-alert1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore2_crit: bigcore2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&bigcore2_alert1>; + cooling-device = + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + /* threshold to start collecting temperature + * statistics e.g. with the IPA governor + */ + littlecore_alert0: littlecore-alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + /* actual control temperature */ + littlecore_alert1: littlecore-alert1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&littlecore_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 6>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; saradc: adc@fec10000 { -- 2.44.0 From 1efcbe97f38b536bd28ce3398caed01ca3fde116 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Thu, 29 Feb 2024 23:26:35 +0400 Subject: [PATCH 2/3] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 By default the CPUs on RK3588 start up in a conservative performance mode. Add frequency and voltage mappings to the device tree to enable dynamic scaling via cpufreq. OPP values are adapted from Radxa's downstream kernel for Rock 5B [1], stripping them down to the minimum frequency and voltage combinations as expected by the generic upstream cpufreq-dt driver, and also dropping those OPPs that don't differ in voltage but only in frequency (keeping the top frequency OPP in each case). Note that this patch ignores voltage scaling for the CPU memory interface which the downstream kernel does through a custom cpufreq driver, and which is why the downstream version has two sets of voltage values for each OPP (the second one being meant for the memory interface supply regulator). This is done instead via regulator coupling between CPU and memory interface supplies on affected boards. This has been tested on Rock 5B with u-boot 2023.11 compiled from Collabora's integration tree [2] with binary bl31 and appears to be stable both under active cooling and passive cooling (with throttling) [1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi [2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240229-rk-dts-additions-v3-4-6afe8473a631@gmail.com Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 56fafb09bcbb..d61bd679ae25 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -97,6 +97,7 @@ cpu_l0: cpu@0 { clocks = <&scmi_clk SCMI_CLK_CPUL>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -116,6 +117,7 @@ cpu_l1: cpu@100 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -135,6 +137,7 @@ cpu_l2: cpu@200 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -154,6 +157,7 @@ cpu_l3: cpu@300 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -175,6 +179,7 @@ cpu_b0: cpu@400 { clocks = <&scmi_clk SCMI_CLK_CPUB01>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -194,6 +199,7 @@ cpu_b1: cpu@500 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; + operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -215,6 +221,7 @@ cpu_b2: cpu@600 { clocks = <&scmi_clk SCMI_CLK_CPUB23>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster2_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -234,6 +241,7 @@ cpu_b3: cpu@700 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; + operating-points-v2 = <&cluster2_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -348,6 +356,120 @@ l3_cache: l3-cache { }; }; + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <712500 712500 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <850000 850000 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + firmware { optee: optee { compatible = "linaro,optee-tz"; -- 2.44.0 From 3da517077233b348d627fcada4337365e2f710f9 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Thu, 29 Feb 2024 23:26:36 +0400 Subject: [PATCH 3/3] arm64: dts: rockchip: Add further granularity in RK3588 CPU OPPs This introduces additional OPPs that share the same voltage as another OPP already present in the .dtsi but with lower frequency. The idea is to try and limit system throughput more gradually upon reaching the throttling condition for workloads that are close to sustainable power already, thus avoiding needless performance loss. My limited synthetic benchmarking [1] showed around 3.8% performance benefit when these are in place, other things equal (not meant to be comprehensive). Though dmesg complains about these OPPs being 'inefficient': [ 9.009561] cpu cpu0: EM: OPP:816000 is inefficient [ 9.009580] cpu cpu0: EM: OPP:600000 is inefficient [ 9.009591] cpu cpu0: EM: OPP:408000 is inefficient [ 9.011370] cpu cpu4: EM: OPP:2352000 is inefficient [ 9.011379] cpu cpu4: EM: OPP:2304000 is inefficient [ 9.011384] cpu cpu4: EM: OPP:2256000 is inefficient [ 9.011389] cpu cpu4: EM: OPP:600000 is inefficient [ 9.011393] cpu cpu4: EM: OPP:408000 is inefficient [ 9.012978] cpu cpu6: EM: OPP:2352000 is inefficient [ 9.012987] cpu cpu6: EM: OPP:2304000 is inefficient [ 9.012992] cpu cpu6: EM: OPP:2256000 is inefficient [ 9.012996] cpu cpu6: EM: OPP:600000 is inefficient [ 9.013000] cpu cpu6: EM: OPP:408000 is inefficient [1] https://lore.kernel.org/linux-rockchip/CABjd4YxqarUCbZ-a2XLe3TWJ-qjphGkyq=wDnctnEhdoSdPPpw@mail.gmail.com/T/#me92aa0ee25e6eeb1d1501ce85f5af4e58b3b13c5 Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20240229-rk-dts-additions-v3-5-6afe8473a631@gmail.com Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 87 +++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index d61bd679ae25..bd57b0a541c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -360,6 +360,21 @@ cluster0_opp_table: opp-table-cluster0 { compatible = "operating-points-v2"; opp-shared; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <675000 675000 950000>; @@ -392,6 +407,27 @@ cluster1_opp_table: opp-table-cluster1 { compatible = "operating-points-v2"; opp-shared; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <675000 675000 1000000>; @@ -422,6 +458,21 @@ opp-2208000000 { opp-microvolt = <987500 987500 1000000>; clock-latency-ns = <40000>; }; + opp-2256000000 { + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000 1000000 1000000>; @@ -433,6 +484,27 @@ cluster2_opp_table: opp-table-cluster2 { compatible = "operating-points-v2"; opp-shared; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <675000 675000 1000000>; @@ -463,6 +535,21 @@ opp-2208000000 { opp-microvolt = <987500 987500 1000000>; clock-latency-ns = <40000>; }; + opp-2256000000 { + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000 1000000 1000000>; -- 2.44.0