From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Wed, 1 Nov 2023 18:50:38 +0200 Subject: [WIP] drm/bridge: synopsys: Add initial support for DW HDMI QP TX Controller Co-developed-by: Algea Cao Signed-off-by: Algea Cao Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/Makefile | 2 +- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 2401 ++++++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 831 +++ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 89 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 4 + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2740 +++++++++- include/drm/bridge/dw_hdmi.h | 101 + 7 files changed, 6102 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile index ce715562e9e5..8354e4879f70 100644 --- a/drivers/gpu/drm/bridge/synopsys/Makefile +++ b/drivers/gpu/drm/bridge/synopsys/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o +obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o dw-hdmi-qp.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c new file mode 100644 index 000000000000..8817ef9a9de9 --- /dev/null +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -0,0 +1,2401 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) Rockchip Electronics Co.Ltd + * Author: + * Algea Cao + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "dw-hdmi-qp.h" + +#define DDC_CI_ADDR 0x37 +#define DDC_SEGMENT_ADDR 0x30 + +#define HDMI_EDID_LEN 512 + +/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ +#define SCDC_MIN_SOURCE_VERSION 0x1 + +#define HDMI14_MAX_TMDSCLK 340000000 +#define HDMI20_MAX_TMDSCLK_KHZ 600000 + +static const unsigned int dw_hdmi_cable[] = { + EXTCON_DISP_HDMI, + EXTCON_NONE, +}; + +static const struct drm_display_mode dw_hdmi_default_modes[] = { + /* 16 - 1920x1080@60Hz 16:9 */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, + 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 2 - 720x480@60Hz 4:3 */ + { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, + 798, 858, 0, 480, 489, 495, 525, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, + /* 4 - 1280x720@60Hz 16:9 */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, + 1430, 1650, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 31 - 1920x1080@50Hz 16:9 */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, + 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 19 - 1280x720@50Hz 16:9 */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, + 1760, 1980, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 17 - 720x576@50Hz 4:3 */ + { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, + 796, 864, 0, 576, 581, 586, 625, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, + /* 2 - 720x480@60Hz 4:3 */ + { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, + 798, 858, 0, 480, 489, 495, 525, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), + .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, +}; + +enum frl_mask { + FRL_3GBPS_3LANE = 1, + FRL_6GBPS_3LANE, + FRL_6GBPS_4LANE, + FRL_8GBPS_4LANE, + FRL_10GBPS_4LANE, + FRL_12GBPS_4LANE, +}; + +struct hdmi_vmode_qp { + bool mdataenablepolarity; + + unsigned int previous_pixelclock; + unsigned long mpixelclock; + unsigned int mpixelrepetitioninput; + unsigned int mpixelrepetitionoutput; + unsigned long previous_tmdsclock; + unsigned int mtmdsclock; +}; + +struct hdmi_qp_data_info { + unsigned int enc_in_bus_format; + unsigned int enc_out_bus_format; + unsigned int enc_in_encoding; + unsigned int enc_out_encoding; + unsigned int quant_range; + unsigned int pix_repet_factor; + struct hdmi_vmode_qp video_mode; + bool update; +}; + +struct dw_hdmi_qp_i2c { + struct i2c_adapter adap; + + struct mutex lock; /* used to serialize data transfers */ + struct completion cmp; + u32 stat; + + u8 slave_reg; + bool is_regaddr; + bool is_segment; + + unsigned int scl_high_ns; + unsigned int scl_low_ns; +}; + +struct dw_hdmi_qp { + struct drm_connector connector; + struct drm_bridge bridge; + struct platform_device *hdcp_dev; + struct platform_device *audio; + struct platform_device *cec; + struct device *dev; + struct dw_hdmi_qp_i2c *i2c; + + struct hdmi_qp_data_info hdmi_data; + const struct dw_hdmi_plat_data *plat_data; + + int vic; + int main_irq; + int avp_irq; + int earc_irq; + + u8 edid[HDMI_EDID_LEN]; + + struct { + const struct dw_hdmi_qp_phy_ops *ops; + const char *name; + void *data; + bool enabled; + } phy; + + struct drm_display_mode previous_mode; + + struct i2c_adapter *ddc; + void __iomem *regs; + bool sink_is_hdmi; + + struct mutex mutex; /* for state below and previous_mode */ + //[CC:] curr_conn should be removed + struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ + enum drm_connector_force force; /* mutex-protected force state */ + bool disabled; /* DRM has disabled our bridge */ + bool bridge_is_on; /* indicates the bridge is on */ + bool rxsense; /* rxsense state */ + u8 phy_mask; /* desired phy int mask settings */ + u8 mc_clkdis; /* clock disable register */ + + u32 scdc_intr; + u32 flt_intr; + //[CC:] remove earc + u32 earc_intr; + + struct dentry *debugfs_dir; + bool scramble_low_rates; + + struct extcon_dev *extcon; + + struct regmap *regm; + + bool initialized; /* hdmi is enabled before bind */ + struct completion flt_cmp; + struct completion earc_cmp; + + hdmi_codec_plugged_cb plugged_cb; + struct device *codec_dev; + enum drm_connector_status last_connector_result; +}; + +static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) +{ + regmap_write(hdmi->regm, offset, val); +} + +static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) +{ + unsigned int val = 0; + + regmap_read(hdmi->regm, offset, &val); + + return val; +} + +static void handle_plugged_change(struct dw_hdmi_qp *hdmi, bool plugged) +{ + if (hdmi->plugged_cb && hdmi->codec_dev) + hdmi->plugged_cb(hdmi->codec_dev, plugged); +} + +static void hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, u32 reg) +{ + regmap_update_bits(hdmi->regm, reg, mask, data); +} + +static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_RGB101010_1X30: + case MEDIA_BUS_FMT_RGB121212_1X36: + case MEDIA_BUS_FMT_RGB161616_1X48: + return true; + + default: + return false; + } +} + +static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_YUV10_1X30: + case MEDIA_BUS_FMT_YUV12_1X36: + case MEDIA_BUS_FMT_YUV16_1X48: + return true; + + default: + return false; + } +} + +static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_UYVY10_1X20: + case MEDIA_BUS_FMT_UYVY12_1X24: + return true; + + default: + return false; + } +} + +static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + case MEDIA_BUS_FMT_UYYVYY12_0_5X36: + case MEDIA_BUS_FMT_UYYVYY16_0_5X48: + return true; + + default: + return false; + } +} + +static int hdmi_bus_fmt_color_depth(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + return 8; + + case MEDIA_BUS_FMT_RGB101010_1X30: + case MEDIA_BUS_FMT_YUV10_1X30: + case MEDIA_BUS_FMT_UYVY10_1X20: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + return 10; + + case MEDIA_BUS_FMT_RGB121212_1X36: + case MEDIA_BUS_FMT_YUV12_1X36: + case MEDIA_BUS_FMT_UYVY12_1X24: + case MEDIA_BUS_FMT_UYYVYY12_0_5X36: + return 12; + + case MEDIA_BUS_FMT_RGB161616_1X48: + case MEDIA_BUS_FMT_YUV16_1X48: + case MEDIA_BUS_FMT_UYYVYY16_0_5X48: + return 16; + + default: + return 0; + } +} + +static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) +{ + /* Software reset */ + hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); + + hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); + + hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); + + /* Clear DONE and ERROR interrupts */ + hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, + MAINUNIT_1_INT_CLEAR); +} + +static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, + unsigned char *buf, unsigned int length) +{ + struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; + int stat; + + if (!i2c->is_regaddr) { + dev_dbg(hdmi->dev, "set read register address to 0\n"); + i2c->slave_reg = 0x00; + i2c->is_regaddr = true; + } + + while (length--) { + reinit_completion(&i2c->cmp); + + hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, + I2CM_INTERFACE_CONTROL0); + + hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, + I2CM_INTERFACE_CONTROL0); + + stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); + if (!stat) { + dev_err(hdmi->dev, "i2c read time out!\n"); + hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); + return -EAGAIN; + } + + /* Check for error condition on the bus */ + if (i2c->stat & I2CM_NACK_RCVD_IRQ) { + dev_err(hdmi->dev, "i2c read err!\n"); + hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); + return -EIO; + } + + *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; + hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); + } + i2c->is_segment = false; + + return 0; +} + +static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, + unsigned char *buf, unsigned int length) +{ + struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; + int stat; + + if (!i2c->is_regaddr) { + /* Use the first write byte as register address */ + i2c->slave_reg = buf[0]; + length--; + buf++; + i2c->is_regaddr = true; + } + + while (length--) { + reinit_completion(&i2c->cmp); + + hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); + hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, + I2CM_INTERFACE_CONTROL0); + hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, + I2CM_INTERFACE_CONTROL0); + + stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); + if (!stat) { + dev_err(hdmi->dev, "i2c write time out!\n"); + hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); + return -EAGAIN; + } + + /* Check for error condition on the bus */ + if (i2c->stat & I2CM_NACK_RCVD_IRQ) { + dev_err(hdmi->dev, "i2c write nack!\n"); + hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); + return -EIO; + } + hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); + } + + return 0; +} + +static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap); + struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; + u8 addr = msgs[0].addr; + int i, ret = 0; + + if (addr == DDC_CI_ADDR) + /* + * The internal I2C controller does not support the multi-byte + * read and write operations needed for DDC/CI. + * TOFIX: Blacklist the DDC/CI address until we filter out + * unsupported I2C operations. + */ + return -EOPNOTSUPP; + + for (i = 0; i < num; i++) { + if (msgs[i].len == 0) { + dev_err(hdmi->dev, + "unsupported transfer %d/%d, no data\n", + i + 1, num); + return -EOPNOTSUPP; + } + } + + mutex_lock(&i2c->lock); + + /* Unmute DONE and ERROR interrupts */ + hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, + I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, + MAINUNIT_1_INT_MASK_N); + + /* Set slave device address taken from the first I2C message */ + if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) + addr = DDC_ADDR; + + hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); + + /* Set slave device register address on transfer */ + i2c->is_regaddr = false; + + /* Set segment pointer for I2C extended read mode operation */ + i2c->is_segment = false; + + for (i = 0; i < num; i++) { + if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { + i2c->is_segment = true; + hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, + I2CM_INTERFACE_CONTROL1); + hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, + I2CM_INTERFACE_CONTROL1); + } else { + if (msgs[i].flags & I2C_M_RD) + ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, + msgs[i].len); + else + ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, + msgs[i].len); + } + if (ret < 0) + break; + } + + if (!ret) + ret = num; + + /* Mute DONE and ERROR interrupts */ + hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, + MAINUNIT_1_INT_MASK_N); + + mutex_unlock(&i2c->lock); + + return ret; +} + +static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm dw_hdmi_algorithm = { + .master_xfer = dw_hdmi_i2c_xfer, + .functionality = dw_hdmi_i2c_func, +}; + +static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi_qp *hdmi) +{ + struct i2c_adapter *adap; + struct dw_hdmi_qp_i2c *i2c; + int ret; + + i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return ERR_PTR(-ENOMEM); + + mutex_init(&i2c->lock); + init_completion(&i2c->cmp); + + adap = &i2c->adap; + adap->owner = THIS_MODULE; + adap->dev.parent = hdmi->dev; + adap->algo = &dw_hdmi_algorithm; + strscpy(adap->name, "ddc", sizeof(adap->name)); + i2c_set_adapdata(adap, hdmi); + + ret = i2c_add_adapter(adap); + if (ret) { + dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); + devm_kfree(hdmi->dev, i2c); + return ERR_PTR(ret); + } + + hdmi->i2c = i2c; + + dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); + + return adap; +} + +#define HDMI_PHY_EARC_MASK BIT(29) + +/* ----------------------------------------------------------------------------- + * HDMI TX Setup + */ + +static void hdmi_infoframe_set_checksum(u8 *ptr, int size) +{ + u8 csum = 0; + int i; + + ptr[3] = 0; + /* compute checksum */ + for (i = 0; i < size; i++) + csum += ptr[i]; + + ptr[3] = 256 - csum; +} + +static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, + const struct drm_connector *connector, + const struct drm_display_mode *mode) +{ + struct hdmi_avi_infoframe frame; + u32 val, i, j; + u8 buff[17]; + enum hdmi_quantization_range rgb_quant_range = + hdmi->hdmi_data.quant_range; + + /* Initialise info frame from DRM mode */ + drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); + + /* + * Ignore monitor selectable quantization, use quantization set + * by the user + */ + drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, rgb_quant_range); + if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) + frame.colorspace = HDMI_COLORSPACE_YUV444; + else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) + frame.colorspace = HDMI_COLORSPACE_YUV422; + else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) + frame.colorspace = HDMI_COLORSPACE_YUV420; + else + frame.colorspace = HDMI_COLORSPACE_RGB; + + /* Set up colorimetry */ + if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { + switch (hdmi->hdmi_data.enc_out_encoding) { + case V4L2_YCBCR_ENC_601: + if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) + frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; + else + frame.colorimetry = HDMI_COLORIMETRY_ITU_601; + frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; + break; + case V4L2_YCBCR_ENC_709: + if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) + frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; + else + frame.colorimetry = HDMI_COLORIMETRY_ITU_709; + frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; + break; + case V4L2_YCBCR_ENC_BT2020: + if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) + frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; + else + frame.colorimetry = HDMI_COLORIMETRY_ITU_709; + frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_BT2020; + break; + default: /* Carries no data */ + frame.colorimetry = HDMI_COLORIMETRY_ITU_601; + frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; + break; + } + } else { + if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { + frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; + frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_BT2020; + } else { + frame.colorimetry = HDMI_COLORIMETRY_NONE; + frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; + } + } + + frame.scan_mode = HDMI_SCAN_MODE_NONE; + frame.video_code = hdmi->vic; + + hdmi_avi_infoframe_pack_only(&frame, buff, 17); + + /* mode which vic >= 128 must use avi version 3 */ + if (hdmi->vic >= 128) { + frame.version = 3; + buff[1] = frame.version; + buff[4] &= 0x1f; + buff[4] |= ((frame.colorspace & 0x7) << 5); + buff[7] = frame.video_code; + hdmi_infoframe_set_checksum(buff, 17); + } + + /* + * The Designware IP uses a different byte format from standard + * AVI info frames, though generally the bits are in the correct + * bytes. + */ + + val = (frame.version << 8) | (frame.length << 16); + hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + if (i * 4 + j >= 14) + break; + if (!j) + val = buff[i * 4 + j + 3]; + val |= buff[i * 4 + j + 3] << (8 * j); + } + + hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); + } + + hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); + + hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, + PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, + PKTSCHED_PKT_EN); +} + +static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi) +{ + u8 ds_type = 0; + u8 sync = 1; + u8 vfr = 1; + u8 afr = 0; + u8 new = 1; + u8 end = 0; + u8 data_set_length = 136; + u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; + u8 *pps_body; + u32 val, i, reg; + struct drm_display_mode *mode = &hdmi->previous_mode; + int hsync, hfront, hback; + struct dw_hdmi_link_config *link_cfg; + void *data = hdmi->plat_data->phy_data; + + hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); + + if (hdmi->plat_data->get_link_cfg) { + link_cfg = hdmi->plat_data->get_link_cfg(data); + } else { + dev_err(hdmi->dev, "can't get frl link cfg\n"); + return; + } + + if (!link_cfg->dsc_mode) { + dev_info(hdmi->dev, "don't use dsc mode\n"); + return; + } + + pps_body = link_cfg->pps_payload; + + hsync = mode->hsync_end - mode->hsync_start; + hback = mode->htotal - mode->hsync_end; + hfront = mode->hsync_start - mode->hdisplay; + + for (i = 0; i < 6; i++) { + val = i << 16 | hb1[i] << 8; + hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); + } + + val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | + vfr << 2 | sync << 1; + hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); + + val = data_set_length << 16 | pps_body[0] << 24; + hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); + + reg = PKT0_EMP_CVTEM_CONTENTS3; + for (i = 1; i < 125; i++) { + if (reg == PKT1_EMP_CVTEM_CONTENTS0 || + reg == PKT2_EMP_CVTEM_CONTENTS0 || + reg == PKT3_EMP_CVTEM_CONTENTS0 || + reg == PKT4_EMP_CVTEM_CONTENTS0 || + reg == PKT5_EMP_CVTEM_CONTENTS0) { + reg += 4; + i--; + continue; + } + if (i % 4 == 1) + val = pps_body[i]; + if (i % 4 == 2) + val |= pps_body[i] << 8; + if (i % 4 == 3) + val |= pps_body[i] << 16; + if (!(i % 4)) { + val |= pps_body[i] << 24; + hdmi_writel(hdmi, val, reg); + reg += 4; + } + } + + val = (hfront & 0xff) << 24 | pps_body[127] << 16 | + pps_body[126] << 8 | pps_body[125]; + hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); + + val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | + (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); + hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); + + val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); + hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); + + for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) + hdmi_writel(hdmi, 0, i); + + hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, + PKTSCHED_PKT_EN); +} + +static void hdmi_config_drm_infoframe(struct dw_hdmi_qp *hdmi, + const struct drm_connector *connector) +{ + const struct drm_connector_state *conn_state = connector->state; + struct hdr_output_metadata *hdr_metadata; + struct hdmi_drm_infoframe frame; + u8 buffer[30]; + ssize_t err; + int i; + u32 val; + + if (!hdmi->plat_data->use_drm_infoframe) + return; + + hdmi_modb(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); + + if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) { + DRM_DEBUG("No need to set HDR metadata in infoframe\n"); + return; + } + + if (!conn_state->hdr_output_metadata) { + DRM_DEBUG("source metadata not set yet\n"); + return; + } + + hdr_metadata = (struct hdr_output_metadata *) + conn_state->hdr_output_metadata->data; + + if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf & + BIT(hdr_metadata->hdmi_metadata_type1.eotf))) { + DRM_ERROR("Not support EOTF %d\n", + hdr_metadata->hdmi_metadata_type1.eotf); + return; + } + + err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); + if (err < 0) + return; + + err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); + if (err < 0) { + dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); + return; + } + + val = (frame.version << 8) | (frame.length << 16); + hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS0); + + for (i = 0; i <= frame.length; i++) { + if (i % 4 == 0) + val = buffer[3 + i]; + val |= buffer[3 + i] << ((i % 4) * 8); + + if (i % 4 == 3 || (i == (frame.length))) + hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS1 + ((i / 4) * 4)); + } + + hdmi_modb(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1); + + hdmi_modb(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); + + DRM_DEBUG("%s eotf %d end\n", __func__, + hdr_metadata->hdmi_metadata_type1.eotf); +} + +/* Filter out invalid setups to avoid configuring SCDC and scrambling */ +static bool dw_hdmi_support_scdc(struct dw_hdmi_qp *hdmi, + const struct drm_display_info *display) +{ + /* Disable if no DDC bus */ + if (!hdmi->ddc) + return false; + + /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ + if (!display->hdmi.scdc.supported || + !display->hdmi.scdc.scrambling.supported) + return false; + + /* + * Disable if display only support low TMDS rates and scrambling + * for low rates is not supported either + */ + if (!display->hdmi.scdc.scrambling.low_rates && + display->max_tmds_clock <= 340000) + return false; + + return true; +} + +static int hdmi_set_frl_mask(int frl_rate) +{ + switch (frl_rate) { + case 48: + return FRL_12GBPS_4LANE; + case 40: + return FRL_10GBPS_4LANE; + case 32: + return FRL_8GBPS_4LANE; + case 24: + return FRL_6GBPS_4LANE; + case 18: + return FRL_6GBPS_3LANE; + case 9: + return FRL_3GBPS_3LANE; + } + + return 0; +} + +static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) +{ + u8 val; + u8 ffe_lv = 0; + int i = 0, stat; + + /* FLT_READY & FFE_LEVELS read */ + for (i = 0; i < 20; i++) { + drm_scdc_readb(hdmi->ddc, SCDC_STATUS_FLAGS_0, &val); + if (val & BIT(6)) + break; + msleep(20); + } + + if (i == 20) { + dev_err(hdmi->dev, "sink flt isn't ready\n"); + return -EINVAL; + } + + hdmi_modb(hdmi, SCDC_UPD_FLAGS_RD_IRQ, SCDC_UPD_FLAGS_RD_IRQ, + MAINUNIT_1_INT_MASK_N); + hdmi_modb(hdmi, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, + SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR, + SCDC_CONFIG0); + + /* max ffe level 3 */ + val = 3 << 4 | hdmi_set_frl_mask(rate); + drm_scdc_writeb(hdmi->ddc, 0x31, val); + + /* select FRL_RATE & FFE_LEVELS */ + hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); + + /* Start LTS_3 state in source DUT */ + reinit_completion(&hdmi->flt_cmp); + hdmi_modb(hdmi, FLT_EXIT_TO_LTSP_IRQ, FLT_EXIT_TO_LTSP_IRQ, + MAINUNIT_1_INT_MASK_N); + hdmi_writel(hdmi, 1, FLT_CONTROL0); + + /* wait for completed link training at source side */ + stat = wait_for_completion_timeout(&hdmi->flt_cmp, HZ * 2); + if (!stat) { + dev_err(hdmi->dev, "wait lts3 finish time out\n"); + hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | + SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); + hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, + MAINUNIT_1_INT_MASK_N); + return -EAGAIN; + } + + if (!(hdmi->flt_intr & FLT_EXIT_TO_LTSP_IRQ)) { + dev_err(hdmi->dev, "not to ltsp\n"); + hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | + SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); + hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, + MAINUNIT_1_INT_MASK_N); + return -EINVAL; + } + + return 0; +} + +#define HDMI_MODE_FRL_MASK BIT(30) + +static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, + struct dw_hdmi_link_config *link_cfg, + const struct drm_connector *connector) +{ + int frl_rate; + int i; + + /* set sink frl mode disable and wait sink ready */ + hdmi_writel(hdmi, 0, FLT_CONFIG0); + if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) + drm_scdc_writeb(hdmi->ddc, 0x31, 0); + /* + * some TVs must wait a while before switching frl mode resolution, + * or the signal may not be recognized. + */ + msleep(200); + + if (!link_cfg->frl_mode) { + dev_info(hdmi->dev, "dw hdmi qp use tmds mode\n"); + hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); + hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); + return; + } + + if (link_cfg->frl_lanes == 4) + hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, + LINK_CONFIG0); + else + hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); + + hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); + + frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; + hdmi_start_flt(hdmi, frl_rate); + + for (i = 0; i < 50; i++) { + hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); + mdelay(1); + hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); + } +} + +static unsigned long +hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) +{ + unsigned long tmdsclock = mpixelclock; + unsigned int depth = + hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); + + if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { + switch (depth) { + case 16: + tmdsclock = mpixelclock * 2; + break; + case 12: + tmdsclock = mpixelclock * 3 / 2; + break; + case 10: + tmdsclock = mpixelclock * 5 / 4; + break; + default: + break; + } + } + + return tmdsclock; +} + +//[CC:] is connector param different from hdmi->connector? +//[CC:] probably it possible to hook the whole implementation into dw-hdmi.c +static int dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi, + struct drm_connector *connector, + struct drm_display_mode *mode) +{ + int ret; + void *data = hdmi->plat_data->phy_data; + struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode; + struct dw_hdmi_link_config *link_cfg; + u8 bytes = 0; + + hdmi->vic = drm_match_cea_mode(mode); + if (!hdmi->vic) + dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); + else + dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); + + if (hdmi->plat_data->get_enc_out_encoding) + hdmi->hdmi_data.enc_out_encoding = + hdmi->plat_data->get_enc_out_encoding(data); + else if ((hdmi->vic == 6) || (hdmi->vic == 7) || + (hdmi->vic == 21) || (hdmi->vic == 22) || + (hdmi->vic == 2) || (hdmi->vic == 3) || + (hdmi->vic == 17) || (hdmi->vic == 18)) + hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; + else + hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; + + if (mode->flags & DRM_MODE_FLAG_DBLCLK) { + hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; + hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; + } else { + hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; + hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; + } + /* Get input format from plat data or fallback to RGB888 */ + if (hdmi->plat_data->get_input_bus_format) + hdmi->hdmi_data.enc_in_bus_format = + hdmi->plat_data->get_input_bus_format(data); + else if (hdmi->plat_data->input_bus_format) + hdmi->hdmi_data.enc_in_bus_format = + hdmi->plat_data->input_bus_format; + else + hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; + + /* Default to RGB888 output format */ + if (hdmi->plat_data->get_output_bus_format) + hdmi->hdmi_data.enc_out_bus_format = + hdmi->plat_data->get_output_bus_format(data); + else + hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; + + /* Get input encoding from plat data or fallback to none */ + if (hdmi->plat_data->get_enc_in_encoding) + hdmi->hdmi_data.enc_in_encoding = + hdmi->plat_data->get_enc_in_encoding(data); + else if (hdmi->plat_data->input_bus_encoding) + hdmi->hdmi_data.enc_in_encoding = + hdmi->plat_data->input_bus_encoding; + else + hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; + + if (hdmi->plat_data->get_quant_range) + hdmi->hdmi_data.quant_range = + hdmi->plat_data->get_quant_range(data); + else + hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; + + if (hdmi->plat_data->get_link_cfg) + link_cfg = hdmi->plat_data->get_link_cfg(data); + else + return -EINVAL; + + hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_MODE_FRL_MASK, + link_cfg->frl_mode); + + /* + * According to the dw-hdmi specification 6.4.2 + * vp_pr_cd[3:0]: + * 0000b: No pixel repetition (pixel sent only once) + * 0001b: Pixel sent two times (pixel repeated once) + */ + hdmi->hdmi_data.pix_repet_factor = + (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; + hdmi->hdmi_data.video_mode.mdataenablepolarity = true; + + vmode->previous_pixelclock = vmode->mpixelclock; + //[CC:] no split mode + // if (hdmi->plat_data->split_mode) + // mode->crtc_clock /= 2; + vmode->mpixelclock = mode->crtc_clock * 1000; + if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) + vmode->mpixelclock *= 2; + dev_dbg(hdmi->dev, "final pixclk = %ld\n", vmode->mpixelclock); + vmode->previous_tmdsclock = vmode->mtmdsclock; + vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); + if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) + vmode->mtmdsclock /= 2; + dev_info(hdmi->dev, "final tmdsclk = %d\n", vmode->mtmdsclock); + + ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); + if (ret) + return ret; + + if (hdmi->plat_data->set_grf_cfg) + hdmi->plat_data->set_grf_cfg(data); + + /* not for DVI mode */ + if (hdmi->sink_is_hdmi) { + dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); + hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); + hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); + if (!link_cfg->frl_mode) { + if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { + drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes); + drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, + min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); + //[CC:] use dw_hdmi_set_high_tmds_clock_ratio() + drm_scdc_set_high_tmds_clock_ratio(connector, 1); + drm_scdc_set_scrambling(connector, 1); + hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); + } else { + if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) { + drm_scdc_set_high_tmds_clock_ratio(connector, 0); + drm_scdc_set_scrambling(connector, 0); + } + hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); + } + } + /* HDMI Initialization Step F - Configure AVI InfoFrame */ + hdmi_config_AVI(hdmi, connector, mode); + hdmi_config_CVTEM(hdmi); + hdmi_config_drm_infoframe(hdmi, connector); + hdmi_set_op_mode(hdmi, link_cfg, connector); + } else { + hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); + hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); + dev_info(hdmi->dev, "%s DVI mode\n", __func__); + } + + return 0; +} + +static enum drm_connector_status +dw_hdmi_connector_detect(struct drm_connector *connector, bool force) +{ + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + struct dw_hdmi_qp *secondary = NULL; + enum drm_connector_status result, result_secondary; + + mutex_lock(&hdmi->mutex); + hdmi->force = DRM_FORCE_UNSPECIFIED; + mutex_unlock(&hdmi->mutex); + + if (hdmi->plat_data->left) + secondary = hdmi->plat_data->left; + else if (hdmi->plat_data->right) + secondary = hdmi->plat_data->right; + + result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); + + if (secondary) { + result_secondary = secondary->phy.ops->read_hpd(secondary, secondary->phy.data); + if (result == connector_status_connected && + result_secondary == connector_status_connected) + result = connector_status_connected; + else + result = connector_status_disconnected; + } + + mutex_lock(&hdmi->mutex); + if (result != hdmi->last_connector_result) { + dev_dbg(hdmi->dev, "read_hpd result: %d", result); + handle_plugged_change(hdmi, + result == connector_status_connected); + hdmi->last_connector_result = result; + } + mutex_unlock(&hdmi->mutex); + + return result; +} + +static int +dw_hdmi_update_hdr_property(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp, + connector); + void *data = hdmi->plat_data->phy_data; + const struct hdr_static_metadata *metadata = + &connector->hdr_sink_metadata.hdmi_type1; + size_t size = sizeof(*metadata); + struct drm_property *property = NULL; + struct drm_property_blob *blob; + int ret; + + if (hdmi->plat_data->get_hdr_property) + property = hdmi->plat_data->get_hdr_property(data); + + if (!property) + return -EINVAL; + + if (hdmi->plat_data->get_hdr_blob) + blob = hdmi->plat_data->get_hdr_blob(data); + else + return -EINVAL; + + ret = drm_property_replace_global_blob(dev, &blob, size, metadata, + &connector->base, property); + return ret; +} + +static int dw_hdmi_connector_get_modes(struct drm_connector *connector) +{ + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + struct hdr_static_metadata *metedata = + &connector->hdr_sink_metadata.hdmi_type1; + struct edid *edid; + struct drm_display_mode *mode; + struct drm_display_info *info = &connector->display_info; + // void *data = hdmi->plat_data->phy_data; + int i, ret = 0; + + if (!hdmi->ddc) + return 0; + + memset(metedata, 0, sizeof(*metedata)); + edid = drm_get_edid(connector, hdmi->ddc); + if (edid) { + dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", + edid->width_cm, edid->height_cm); + + hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); + drm_connector_update_edid_property(connector, edid); + // if (hdmi->plat_data->get_edid_dsc_info) + // hdmi->plat_data->get_edid_dsc_info(data, edid); + ret = drm_add_edid_modes(connector, edid); + dw_hdmi_update_hdr_property(connector); + // if (ret > 0 && hdmi->plat_data->split_mode) { + // struct dw_hdmi_qp *secondary = NULL; + // void *secondary_data; + // + // if (hdmi->plat_data->left) + // secondary = hdmi->plat_data->left; + // else if (hdmi->plat_data->right) + // secondary = hdmi->plat_data->right; + // + // if (!secondary) + // return -ENOMEM; + // secondary_data = secondary->plat_data->phy_data; + // + // list_for_each_entry(mode, &connector->probed_modes, head) + // hdmi->plat_data->convert_to_split_mode(mode); + // + // secondary->sink_is_hdmi = drm_detect_hdmi_monitor(edid); + // if (secondary->plat_data->get_edid_dsc_info) + // secondary->plat_data->get_edid_dsc_info(secondary_data, edid); + // } + kfree(edid); + } else { + hdmi->sink_is_hdmi = true; + + if (hdmi->plat_data->split_mode) { + if (hdmi->plat_data->left) { + hdmi->plat_data->left->sink_is_hdmi = true; + } else if (hdmi->plat_data->right) { + hdmi->plat_data->right->sink_is_hdmi = true; + } + } + + for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) { + const struct drm_display_mode *ptr = + &dw_hdmi_default_modes[i]; + + mode = drm_mode_duplicate(connector->dev, ptr); + if (mode) { + if (!i) + mode->type = DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, mode); + ret++; + } + } + if (ret > 0 && hdmi->plat_data->split_mode) { + struct drm_display_mode *mode; + + list_for_each_entry(mode, &connector->probed_modes, head) + hdmi->plat_data->convert_to_split_mode(mode); + } + info->edid_hdmi_rgb444_dc_modes = 0; + info->hdmi.y420_dc_modes = 0; + info->color_formats = 0; + + dev_info(hdmi->dev, "failed to get edid\n"); + } + + return ret; +} + +static int +dw_hdmi_atomic_connector_set_property(struct drm_connector *connector, + struct drm_connector_state *state, + struct drm_property *property, + uint64_t val) +{ + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops; + + if (ops && ops->set_property) + return ops->set_property(connector, state, property, + val, hdmi->plat_data->phy_data); + else + return -EINVAL; +} + +static int +dw_hdmi_atomic_connector_get_property(struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops; + + if (ops && ops->get_property) + return ops->get_property(connector, state, property, + val, hdmi->plat_data->phy_data); + else + return -EINVAL; +} + +static int +dw_hdmi_connector_set_property(struct drm_connector *connector, + struct drm_property *property, uint64_t val) +{ + return dw_hdmi_atomic_connector_set_property(connector, NULL, + property, val); +} + +static void dw_hdmi_attach_properties(struct dw_hdmi_qp *hdmi) +{ + unsigned int color = MEDIA_BUS_FMT_RGB888_1X24; + const struct dw_hdmi_property_ops *ops = + hdmi->plat_data->property_ops; + + if (ops && ops->attach_properties) + return ops->attach_properties(&hdmi->connector, color, 0, + hdmi->plat_data->phy_data); +} + +static void dw_hdmi_destroy_properties(struct dw_hdmi_qp *hdmi) +{ + const struct dw_hdmi_property_ops *ops = + hdmi->plat_data->property_ops; + + if (ops && ops->destroy_properties) + return ops->destroy_properties(&hdmi->connector, + hdmi->plat_data->phy_data); +} + +static struct drm_encoder * +dw_hdmi_connector_best_encoder(struct drm_connector *connector) +{ + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + + return hdmi->bridge.encoder; +} + +static bool dw_hdmi_color_changed(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + void *data = hdmi->plat_data->phy_data; + struct drm_connector_state *old_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_connector_state *new_state = + drm_atomic_get_new_connector_state(state, connector); + bool ret = false; + + if (hdmi->plat_data->get_color_changed) + ret = hdmi->plat_data->get_color_changed(data); + + if (new_state->colorspace != old_state->colorspace) + ret = true; + + return ret; +} + +static bool hdr_metadata_equal(const struct drm_connector_state *old_state, + const struct drm_connector_state *new_state) +{ + struct drm_property_blob *old_blob = old_state->hdr_output_metadata; + struct drm_property_blob *new_blob = new_state->hdr_output_metadata; + + if (!old_blob || !new_blob) + return old_blob == new_blob; + + if (old_blob->length != new_blob->length) + return false; + + return !memcmp(old_blob->data, new_blob->data, old_blob->length); +} + +static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_connector_state *old_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_connector_state *new_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_crtc *crtc = new_state->crtc; + struct drm_crtc_state *crtc_state; + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + struct drm_display_mode *mode = NULL; + void *data = hdmi->plat_data->phy_data; + struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode; + + if (!crtc) + return 0; + + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + /* + * If HDMI is enabled in uboot, it's need to record + * drm_display_mode and set phy status to enabled. + */ + if (!vmode->mpixelclock) { + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (hdmi->plat_data->get_enc_in_encoding) + hdmi->hdmi_data.enc_in_encoding = + hdmi->plat_data->get_enc_in_encoding(data); + if (hdmi->plat_data->get_enc_out_encoding) + hdmi->hdmi_data.enc_out_encoding = + hdmi->plat_data->get_enc_out_encoding(data); + if (hdmi->plat_data->get_input_bus_format) + hdmi->hdmi_data.enc_in_bus_format = + hdmi->plat_data->get_input_bus_format(data); + if (hdmi->plat_data->get_output_bus_format) + hdmi->hdmi_data.enc_out_bus_format = + hdmi->plat_data->get_output_bus_format(data); + + mode = &crtc_state->mode; + if (hdmi->plat_data->split_mode) { + hdmi->plat_data->convert_to_origin_mode(mode); + mode->crtc_clock /= 2; + } + memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); + vmode->mpixelclock = mode->crtc_clock * 1000; + vmode->previous_pixelclock = mode->clock; + vmode->previous_tmdsclock = mode->clock; + vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, + vmode->mpixelclock); + if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) + vmode->mtmdsclock /= 2; + } + + if (!hdr_metadata_equal(old_state, new_state) || + dw_hdmi_color_changed(connector, state)) { + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + crtc_state->mode_changed = true; + } + + return 0; +} + +static void dw_hdmi_connector_force(struct drm_connector *connector) +{ + struct dw_hdmi_qp *hdmi = + container_of(connector, struct dw_hdmi_qp, connector); + + mutex_lock(&hdmi->mutex); + + if (hdmi->force != connector->force) { + if (!hdmi->disabled && connector->force == DRM_FORCE_OFF) + extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, + false); + else if (hdmi->disabled && connector->force == DRM_FORCE_ON) + extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, + true); + } + + hdmi->force = connector->force; + mutex_unlock(&hdmi->mutex); +} + +static int dw_hdmi_qp_fill_modes(struct drm_connector *connector, u32 max_x, + u32 max_y) +{ + return drm_helper_probe_single_connector_modes(connector, 9000, 9000); +} + +static const struct drm_connector_funcs dw_hdmi_connector_funcs = { + .fill_modes = dw_hdmi_qp_fill_modes, + .detect = dw_hdmi_connector_detect, + .destroy = drm_connector_cleanup, + .force = dw_hdmi_connector_force, + .reset = drm_atomic_helper_connector_reset, + .set_property = dw_hdmi_connector_set_property, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .atomic_set_property = dw_hdmi_atomic_connector_set_property, + .atomic_get_property = dw_hdmi_atomic_connector_get_property, +}; + +static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { + .get_modes = dw_hdmi_connector_get_modes, + .best_encoder = dw_hdmi_connector_best_encoder, + .atomic_check = dw_hdmi_connector_atomic_check, +}; + +static int dw_hdmi_qp_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; + struct drm_encoder *encoder = bridge->encoder; + struct drm_connector *connector = &hdmi->connector; + + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) + return 0; + + connector->interlace_allowed = 1; + connector->polled = DRM_CONNECTOR_POLL_HPD; + + drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); + + // [CC:] use drm_connector_init_with_ddc or drmm_connector_init + // to provide ddc reference + drm_connector_init_with_ddc(bridge->dev, connector, + &dw_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA, + hdmi->ddc); + + drm_connector_attach_encoder(connector, encoder); + dw_hdmi_attach_properties(hdmi); + + return 0; +} + +static void dw_hdmi_qp_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *orig_mode, + const struct drm_display_mode *mode) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; + + mutex_lock(&hdmi->mutex); + + /* Store the display mode for plugin/DKMS poweron events */ + memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); + if (hdmi->plat_data->split_mode) + hdmi->plat_data->convert_to_origin_mode(&hdmi->previous_mode); + + mutex_unlock(&hdmi->mutex); +} + +static enum drm_mode_status +dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + return MODE_OK; +} + +static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_state) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; + struct drm_atomic_state *state = old_state->base.state; + struct drm_connector *connector; + + connector = drm_atomic_get_new_connector_for_encoder(state, + bridge->encoder); + + mutex_lock(&hdmi->mutex); + hdmi->curr_conn = connector; + dw_hdmi_qp_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); + hdmi->disabled = false; + mutex_unlock(&hdmi->mutex); + + extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true); + handle_plugged_change(hdmi, true); +} + +static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_state) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; + + extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false); + handle_plugged_change(hdmi, false); + mutex_lock(&hdmi->mutex); + + hdmi->curr_conn = NULL; + + if (hdmi->phy.ops->disable) + hdmi->phy.ops->disable(hdmi, hdmi->phy.data); + hdmi->disabled = true; + mutex_unlock(&hdmi->mutex); +} + +static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .attach = dw_hdmi_qp_bridge_attach, + .mode_set = dw_hdmi_qp_bridge_mode_set, + .mode_valid = dw_hdmi_qp_bridge_mode_valid, + .atomic_enable = dw_hdmi_qp_bridge_atomic_enable, + .atomic_disable = dw_hdmi_qp_bridge_atomic_disable, +}; + +static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi = dev_id; + struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; + u32 stat; + + stat = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS); + + i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | + I2CM_NACK_RCVD_IRQ); + hdmi->scdc_intr = stat & (SCDC_UPD_FLAGS_RD_IRQ | + SCDC_UPD_FLAGS_CHG_IRQ | + SCDC_UPD_FLAGS_CLR_IRQ | + SCDC_RR_REPLY_STOP_IRQ | + SCDC_NACK_RCVD_IRQ); + hdmi->flt_intr = stat & (FLT_EXIT_TO_LTSP_IRQ | + FLT_EXIT_TO_LTS4_IRQ | + FLT_EXIT_TO_LTSL_IRQ); + + if (i2c->stat) { + hdmi_writel(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR); + complete(&i2c->cmp); + } + + if (hdmi->flt_intr) { + dev_dbg(hdmi->dev, "i2c flt irq:%#x\n", hdmi->flt_intr); + hdmi_writel(hdmi, hdmi->flt_intr, MAINUNIT_1_INT_CLEAR); + complete(&hdmi->flt_cmp); + } + + if (hdmi->scdc_intr) { + u8 val; + + dev_dbg(hdmi->dev, "i2c scdc irq:%#x\n", hdmi->scdc_intr); + hdmi_writel(hdmi, hdmi->scdc_intr, MAINUNIT_1_INT_CLEAR); + val = hdmi_readl(hdmi, SCDC_STATUS0); + + /* frl start */ + if (val & BIT(4)) { + hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | + SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); + hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, + MAINUNIT_1_INT_MASK_N); + dev_info(hdmi->dev, "frl start\n"); + } + + } + + if (stat) + return IRQ_HANDLED; + + return IRQ_NONE; +} + +static irqreturn_t dw_hdmi_qp_avp_hardirq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi = dev_id; + u32 stat; + + stat = hdmi_readl(hdmi, AVP_1_INT_STATUS); + if (stat) { + dev_dbg(hdmi->dev, "HDCP irq %#x\n", stat); + stat &= ~stat; + hdmi_writel(hdmi, stat, AVP_1_INT_MASK_N); + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static irqreturn_t dw_hdmi_qp_earc_hardirq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi = dev_id; + u32 stat; + + stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS); + if (stat) { + dev_dbg(hdmi->dev, "earc irq %#x\n", stat); + stat &= ~stat; + hdmi_writel(hdmi, stat, EARCRX_0_INT_MASK_N); + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static irqreturn_t dw_hdmi_qp_avp_irq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi = dev_id; + u32 stat; + + stat = hdmi_readl(hdmi, AVP_1_INT_STATUS); + + if (!stat) + return IRQ_NONE; + + hdmi_writel(hdmi, stat, AVP_1_INT_CLEAR); + + return IRQ_HANDLED; +} + +static irqreturn_t dw_hdmi_qp_earc_irq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi = dev_id; + u32 stat; + + stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS); + + if (!stat) + return IRQ_NONE; + + hdmi_writel(hdmi, stat, EARCRX_0_INT_CLEAR); + + hdmi->earc_intr = stat; + complete(&hdmi->earc_cmp); + + return IRQ_HANDLED; +} + +static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) +{ + u8 phy_type; + + phy_type = hdmi->plat_data->phy_force_vendor ? + DW_HDMI_PHY_VENDOR_PHY : 0; + + if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { + /* Vendor PHYs require support from the glue layer. */ + if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { + dev_err(hdmi->dev, + "Vendor HDMI PHY not supported by glue layer\n"); + return -ENODEV; + } + + hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; + hdmi->phy.data = hdmi->plat_data->phy_data; + hdmi->phy.name = hdmi->plat_data->phy_name; + } + + return 0; +} + +static const struct regmap_config hdmi_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = EARCRX_1_INT_FORCE, +}; + +struct dw_hdmi_qp_reg_table { + int reg_base; + int reg_end; +}; + +static const struct dw_hdmi_qp_reg_table hdmi_reg_table[] = { + {0x0, 0xc}, + {0x14, 0x1c}, + {0x44, 0x48}, + {0x50, 0x58}, + {0x80, 0x84}, + {0xa0, 0xc4}, + {0xe0, 0xe8}, + {0xf0, 0x118}, + {0x140, 0x140}, + {0x150, 0x150}, + {0x160, 0x168}, + {0x180, 0x180}, + {0x800, 0x800}, + {0x808, 0x808}, + {0x814, 0x814}, + {0x81c, 0x824}, + {0x834, 0x834}, + {0x840, 0x864}, + {0x86c, 0x86c}, + {0x880, 0x89c}, + {0x8e0, 0x8e8}, + {0x900, 0x900}, + {0x908, 0x90c}, + {0x920, 0x938}, + {0x920, 0x938}, + {0x960, 0x960}, + {0x968, 0x968}, + {0xa20, 0xa20}, + {0xa30, 0xa30}, + {0xa40, 0xa40}, + {0xa54, 0xa54}, + {0xa80, 0xaac}, + {0xab4, 0xab8}, + {0xb00, 0xcbc}, + {0xce0, 0xce0}, + {0xd00, 0xddc}, + {0xe20, 0xe24}, + {0xe40, 0xe44}, + {0xe4c, 0xe4c}, + {0xe60, 0xe80}, + {0xea0, 0xf24}, + {0x1004, 0x100c}, + {0x1020, 0x1030}, + {0x1040, 0x1050}, + {0x1060, 0x1068}, + {0x1800, 0x1820}, + {0x182c, 0x182c}, + {0x1840, 0x1940}, + {0x1960, 0x1a60}, + {0x1b00, 0x1b00}, + {0x1c00, 0x1c00}, + {0x3000, 0x3000}, + {0x3010, 0x3014}, + {0x3020, 0x3024}, + {0x3800, 0x3800}, + {0x3810, 0x3814}, + {0x3820, 0x3824}, + {0x3830, 0x3834}, + {0x3840, 0x3844}, + {0x3850, 0x3854}, + {0x3860, 0x3864}, + {0x3870, 0x3874}, + {0x4000, 0x4004}, + {0x4800, 0x4800}, + {0x4810, 0x4814}, +}; + +static int dw_hdmi_ctrl_show(struct seq_file *s, void *v) +{ + struct dw_hdmi_qp *hdmi = s->private; + u32 i = 0, j = 0, val = 0; + + seq_puts(s, "\n---------------------------------------------------"); + + for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) { + for (j = hdmi_reg_table[i].reg_base; + j <= hdmi_reg_table[i].reg_end; j += 4) { + val = hdmi_readl(hdmi, j); + + if ((j - hdmi_reg_table[i].reg_base) % 16 == 0) + seq_printf(s, "\n>>>hdmi_ctl %04x:", j); + seq_printf(s, " %08x", val); + } + } + seq_puts(s, "\n---------------------------------------------------\n"); + + return 0; +} + +static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file) +{ + return single_open(file, dw_hdmi_ctrl_show, inode->i_private); +} + +static ssize_t +dw_hdmi_ctrl_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dw_hdmi_qp *hdmi = + ((struct seq_file *)file->private_data)->private; + u32 reg, val; + char kbuf[25]; + + if (count > 24) { + dev_err(hdmi->dev, "out of buf range\n"); + return count; + } + + if (copy_from_user(kbuf, buf, count)) + return -EFAULT; + kbuf[count - 1] = '\0'; + + if (sscanf(kbuf, "%x %x", ®, &val) == -1) + return -EFAULT; + if (reg > EARCRX_1_INT_FORCE) { + dev_err(hdmi->dev, "it is no a hdmi register\n"); + return count; + } + dev_info(hdmi->dev, "/**********hdmi register config******/"); + dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val); + hdmi_writel(hdmi, val, reg); + return count; +} + +static const struct file_operations dw_hdmi_ctrl_fops = { + .owner = THIS_MODULE, + .open = dw_hdmi_ctrl_open, + .read = seq_read, + .write = dw_hdmi_ctrl_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int dw_hdmi_status_show(struct seq_file *s, void *v) +{ + struct dw_hdmi_qp *hdmi = s->private; + u32 val; + + seq_puts(s, "PHY: "); + if (hdmi->disabled) { + seq_puts(s, "disabled\n"); + return 0; + } + seq_puts(s, "enabled\t\t\tMode: "); + if (hdmi->sink_is_hdmi) + seq_puts(s, "HDMI\n"); + else + seq_puts(s, "DVI\n"); + + if (hdmi->hdmi_data.video_mode.mpixelclock > 600000000) { + seq_printf(s, "FRL Mode Pixel Clk: %luHz\n", + hdmi->hdmi_data.video_mode.mpixelclock); + } else { + if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000) + val = hdmi->hdmi_data.video_mode.mtmdsclock / 4; + else + val = hdmi->hdmi_data.video_mode.mtmdsclock; + seq_printf(s, "TMDS Mode Pixel Clk: %luHz\t\tTMDS Clk: %uHz\n", + hdmi->hdmi_data.video_mode.mpixelclock, val); + } + + seq_puts(s, "Color Format: "); + if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) + seq_puts(s, "RGB"); + else if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) + seq_puts(s, "YUV444"); + else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) + seq_puts(s, "YUV422"); + else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) + seq_puts(s, "YUV420"); + else + seq_puts(s, "UNKNOWN"); + val = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); + seq_printf(s, "\t\tColor Depth: %d bit\n", val); + seq_puts(s, "Colorimetry: "); + switch (hdmi->hdmi_data.enc_out_encoding) { + case V4L2_YCBCR_ENC_601: + seq_puts(s, "ITU.BT601"); + break; + case V4L2_YCBCR_ENC_709: + seq_puts(s, "ITU.BT709"); + break; + case V4L2_YCBCR_ENC_BT2020: + seq_puts(s, "ITU.BT2020"); + break; + default: /* Carries no data */ + seq_puts(s, "ITU.BT601"); + break; + } + + seq_puts(s, "\t\tEOTF: "); + + val = hdmi_readl(hdmi, PKTSCHED_PKT_EN); + if (!(val & PKTSCHED_DRMI_TX_EN)) { + seq_puts(s, "Off\n"); + return 0; + } + + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS1); + val = (val >> 8) & 0x7; + switch (val) { + case HDMI_EOTF_TRADITIONAL_GAMMA_SDR: + seq_puts(s, "SDR"); + break; + case HDMI_EOTF_TRADITIONAL_GAMMA_HDR: + seq_puts(s, "HDR"); + break; + case HDMI_EOTF_SMPTE_ST2084: + seq_puts(s, "ST2084"); + break; + case HDMI_EOTF_BT_2100_HLG: + seq_puts(s, "HLG"); + break; + default: + seq_puts(s, "Not Defined\n"); + return 0; + } + + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS1); + val = (val >> 16) & 0xffff; + seq_printf(s, "\nx0: %d", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS2); + val = val & 0xffff; + seq_printf(s, "\t\t\t\ty0: %d\n", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS2); + val = (val >> 16) & 0xffff; + seq_printf(s, "x1: %d", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS3); + val = val & 0xffff; + seq_printf(s, "\t\t\t\ty1: %d\n", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS3); + val = (val >> 16) & 0xffff; + seq_printf(s, "x2: %d", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS4); + val = val & 0xffff; + seq_printf(s, "\t\t\t\ty2: %d\n", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS4); + val = (val >> 16) & 0xffff; + seq_printf(s, "white x: %d", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS5); + val = val & 0xffff; + seq_printf(s, "\t\t\twhite y: %d\n", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS5); + val = (val >> 16) & 0xffff; + seq_printf(s, "max lum: %d", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS6); + val = val & 0xffff; + seq_printf(s, "\t\t\tmin lum: %d\n", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS6); + val = (val >> 16) & 0xffff; + seq_printf(s, "max cll: %d", val); + val = hdmi_readl(hdmi, PKT_DRMI_CONTENTS7); + val = val & 0xffff; + seq_printf(s, "\t\t\tmax fall: %d\n", val); + return 0; +} + +static int dw_hdmi_status_open(struct inode *inode, struct file *file) +{ + return single_open(file, dw_hdmi_status_show, inode->i_private); +} + +static const struct file_operations dw_hdmi_status_fops = { + .owner = THIS_MODULE, + .open = dw_hdmi_status_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi_qp *hdmi) +{ + u8 buf[11]; + + snprintf(buf, sizeof(buf), "dw-hdmi%d", hdmi->plat_data->id); + hdmi->debugfs_dir = debugfs_create_dir(buf, NULL); + if (IS_ERR(hdmi->debugfs_dir)) { + dev_err(dev, "failed to create debugfs dir!\n"); + return; + } + + debugfs_create_file("status", 0400, hdmi->debugfs_dir, + hdmi, &dw_hdmi_status_fops); + debugfs_create_file("ctrl", 0600, hdmi->debugfs_dir, + hdmi, &dw_hdmi_ctrl_fops); +} + +static struct dw_hdmi_qp * +__dw_hdmi_probe(struct platform_device *pdev, + const struct dw_hdmi_plat_data *plat_data) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *ddc_node; + struct dw_hdmi_qp *hdmi; + struct resource *iores = NULL; + int irq; + int ret; + + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return ERR_PTR(-ENOMEM); + + hdmi->connector.stereo_allowed = 1; + hdmi->plat_data = plat_data; + hdmi->dev = dev; + hdmi->disabled = true; + + mutex_init(&hdmi->mutex); + + ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); + if (ddc_node) { + hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); + of_node_put(ddc_node); + if (!hdmi->ddc) { + dev_dbg(hdmi->dev, "failed to read ddc node\n"); + return ERR_PTR(-EPROBE_DEFER); + } + + } else { + dev_dbg(hdmi->dev, "no ddc property found\n"); + } + + if (!plat_data->regm) { + const struct regmap_config *reg_config; + + reg_config = &hdmi_regmap_config; + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + hdmi->regs = devm_ioremap_resource(dev, iores); + if (IS_ERR(hdmi->regs)) { + ret = PTR_ERR(hdmi->regs); + goto err_res; + } + + hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); + if (IS_ERR(hdmi->regm)) { + dev_err(dev, "Failed to configure regmap\n"); + ret = PTR_ERR(hdmi->regm); + goto err_res; + } + } else { + hdmi->regm = plat_data->regm; + } + + ret = dw_hdmi_detect_phy(hdmi); + if (ret < 0) + goto err_res; + + hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); + hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); + hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); + if ((hdmi_readl(hdmi, CMU_STATUS) & DISPLAY_CLK_MONITOR) == DISPLAY_CLK_LOCKED) { + hdmi->initialized = true; + hdmi->disabled = false; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + ret = irq; + goto err_res; + } + + hdmi->avp_irq = irq; + ret = devm_request_threaded_irq(dev, hdmi->avp_irq, + dw_hdmi_qp_avp_hardirq, + dw_hdmi_qp_avp_irq, IRQF_SHARED, + dev_name(dev), hdmi); + if (ret) + goto err_res; + + irq = platform_get_irq(pdev, 1); + if (irq < 0) { + ret = irq; + goto err_res; + } + + irq = platform_get_irq(pdev, 2); + if (irq < 0) { + ret = irq; + goto err_res; + } + + hdmi->earc_irq = irq; + ret = devm_request_threaded_irq(dev, hdmi->earc_irq, + dw_hdmi_qp_earc_hardirq, + dw_hdmi_qp_earc_irq, IRQF_SHARED, + dev_name(dev), hdmi); + if (ret) + goto err_res; + + irq = platform_get_irq(pdev, 3); + if (irq < 0) { + ret = irq; + goto err_res; + } + + hdmi->main_irq = irq; + ret = devm_request_threaded_irq(dev, hdmi->main_irq, + dw_hdmi_qp_main_hardirq, NULL, + IRQF_SHARED, dev_name(dev), hdmi); + if (ret) + goto err_res; + + /* If DDC bus is not specified, try to register HDMI I2C bus */ + if (!hdmi->ddc) { + hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); + if (IS_ERR(hdmi->ddc)) + hdmi->ddc = NULL; + /* + * Read high and low time from device tree. If not available use + * the default timing scl clock rate is about 99.6KHz. + */ + if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns", + &hdmi->i2c->scl_high_ns)) + hdmi->i2c->scl_high_ns = 4708; + if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns", + &hdmi->i2c->scl_low_ns)) + hdmi->i2c->scl_low_ns = 4916; + } + + hdmi->bridge.driver_private = hdmi; + hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; +#ifdef CONFIG_OF + hdmi->bridge.of_node = pdev->dev.of_node; +#endif + + if (hdmi->phy.ops->setup_hpd) + hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); + + hdmi->connector.ycbcr_420_allowed = hdmi->plat_data->ycbcr_420_allowed; + + hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable); + if (IS_ERR(hdmi->extcon)) { + dev_err(hdmi->dev, "allocate extcon failed\n"); + ret = PTR_ERR(hdmi->extcon); + goto err_res; + } + + ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon); + if (ret) { + dev_err(hdmi->dev, "failed to register extcon: %d\n", ret); + goto err_res; + } + + ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI, + EXTCON_PROP_DISP_HPD); + if (ret) { + dev_err(hdmi->dev, + "failed to set USB property capability: %d\n", ret); + goto err_res; + } + + /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ + if (hdmi->i2c) + dw_hdmi_i2c_init(hdmi); + + init_completion(&hdmi->flt_cmp); + init_completion(&hdmi->earc_cmp); + + if (of_property_read_bool(np, "scramble-low-rates")) + hdmi->scramble_low_rates = true; + + dw_hdmi_register_debugfs(dev, hdmi); + + return hdmi; + +err_res: + if (hdmi->i2c) + i2c_del_adapter(&hdmi->i2c->adap); + else + i2c_put_adapter(hdmi->ddc); + + return ERR_PTR(ret); +} + +static void __dw_hdmi_remove(struct dw_hdmi_qp *hdmi) +{ + if (hdmi->avp_irq) + disable_irq(hdmi->avp_irq); + + if (hdmi->main_irq) + disable_irq(hdmi->main_irq); + + if (hdmi->earc_irq) + disable_irq(hdmi->earc_irq); + + debugfs_remove_recursive(hdmi->debugfs_dir); + + if (!hdmi->plat_data->first_screen) { + dw_hdmi_destroy_properties(hdmi); + hdmi->connector.funcs->destroy(&hdmi->connector); + } + + if (hdmi->audio && !IS_ERR(hdmi->audio)) + platform_device_unregister(hdmi->audio); + + // [CC:] dw_hdmi_rockchip_unbind() also calls drm_encoder_cleanup() + // and causes a seg fault due to NULL ptr dererence + // if (hdmi->bridge.encoder && !hdmi->plat_data->first_screen) + // hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder); + // + if (!IS_ERR(hdmi->cec)) + platform_device_unregister(hdmi->cec); + if (hdmi->i2c) + i2c_del_adapter(&hdmi->i2c->adap); + else + i2c_put_adapter(hdmi->ddc); +} + +/* ----------------------------------------------------------------------------- + * Bind/unbind API, used from platforms based on the component framework. + */ +struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, + struct drm_encoder *encoder, + struct dw_hdmi_plat_data *plat_data) +{ + struct dw_hdmi_qp *hdmi; + int ret; + + hdmi = __dw_hdmi_probe(pdev, plat_data); + if (IS_ERR(hdmi)) + return hdmi; + + if (!plat_data->first_screen) { + ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); + if (ret) { + __dw_hdmi_remove(hdmi); + dev_err(hdmi->dev, "Failed to initialize bridge with drm\n"); + return ERR_PTR(ret); + } + + plat_data->connector = &hdmi->connector; + } + + if (plat_data->split_mode && !hdmi->plat_data->first_screen) { + struct dw_hdmi_qp *secondary = NULL; + + if (hdmi->plat_data->left) + secondary = hdmi->plat_data->left; + else if (hdmi->plat_data->right) + secondary = hdmi->plat_data->right; + + if (!secondary) + return ERR_PTR(-ENOMEM); + ret = drm_bridge_attach(encoder, &secondary->bridge, &hdmi->bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) + return ERR_PTR(ret); + } + + return hdmi; +} +EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); + +void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi) +{ + __dw_hdmi_remove(hdmi); +} +EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind); + +void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi) +{ + if (!hdmi) { + dev_warn(dev, "Hdmi has not been initialized\n"); + return; + } + + mutex_lock(&hdmi->mutex); + + /* + * When system shutdown, hdmi should be disabled. + * When system suspend, dw_hdmi_qp_bridge_disable will disable hdmi first. + * To prevent duplicate operation, we should determine whether hdmi + * has been disabled. + */ + if (!hdmi->disabled) + hdmi->disabled = true; + mutex_unlock(&hdmi->mutex); + + if (hdmi->avp_irq) + disable_irq(hdmi->avp_irq); + + if (hdmi->main_irq) + disable_irq(hdmi->main_irq); + + if (hdmi->earc_irq) + disable_irq(hdmi->earc_irq); + + pinctrl_pm_select_sleep_state(dev); +} +EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend); + +void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) +{ + if (!hdmi) { + dev_warn(dev, "Hdmi has not been initialized\n"); + return; + } + + hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); + hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); + hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); + + pinctrl_pm_select_default_state(dev); + + mutex_lock(&hdmi->mutex); + if (hdmi->i2c) + dw_hdmi_i2c_init(hdmi); + if (hdmi->avp_irq) + enable_irq(hdmi->avp_irq); + + if (hdmi->main_irq) + enable_irq(hdmi->main_irq); + + if (hdmi->earc_irq) + enable_irq(hdmi->earc_irq); + + mutex_unlock(&hdmi->mutex); +} +EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume); + +MODULE_AUTHOR("Algea Cao "); +MODULE_DESCRIPTION("DW HDMI QP transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:dw-hdmi-qp"); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h new file mode 100644 index 000000000000..4cac70f2d11d --- /dev/null +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h @@ -0,0 +1,831 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) Rockchip Electronics Co.Ltd + * Author: + * Algea Cao + */ +#ifndef __DW_HDMI_QP_H__ +#define __DW_HDMI_QP_H__ +/* Main Unit Registers */ +#define CORE_ID 0x0 +#define VER_NUMBER 0x4 +#define VER_TYPE 0x8 +#define CONFIG_REG 0xc +#define CONFIG_CEC BIT(28) +#define CONFIG_AUD_UD BIT(23) +#define CORE_TIMESTAMP_HHMM 0x14 +#define CORE_TIMESTAMP_MMDD 0x18 +#define CORE_TIMESTAMP_YYYY 0x1c +/* Reset Manager Registers */ +#define GLOBAL_SWRESET_REQUEST 0x40 +#define EARCRX_CMDC_SWINIT_P BIT(27) +#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) +#define GLOBAL_SWDISABLE 0x44 +#define CEC_SWDISABLE BIT(17) +#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) +#define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) +#define RESET_MANAGER_CONFIG0 0x48 +#define RESET_MANAGER_STATUS0 0x50 +#define RESET_MANAGER_STATUS1 0x54 +#define RESET_MANAGER_STATUS2 0x58 +/* Timer Base Registers */ +#define TIMER_BASE_CONFIG0 0x80 +#define TIMER_BASE_STATUS0 0x84 +/* CMU Registers */ +#define CMU_CONFIG0 0xa0 +#define CMU_CONFIG1 0xa4 +#define CMU_CONFIG2 0xa8 +#define CMU_CONFIG3 0xac +#define CMU_STATUS 0xb0 +#define DISPLAY_CLK_MONITOR 0x3f +#define DISPLAY_CLK_LOCKED 0X15 +#define EARC_BPCLK_OFF BIT(9) +#define AUDCLK_OFF BIT(7) +#define LINKQPCLK_OFF BIT(5) +#define VIDQPCLK_OFF BIT(3) +#define IPI_CLK_OFF BIT(1) +#define CMU_IPI_CLK_FREQ 0xb4 +#define CMU_VIDQPCLK_FREQ 0xb8 +#define CMU_LINKQPCLK_FREQ 0xbc +#define CMU_AUDQPCLK_FREQ 0xc0 +#define CMU_EARC_BPCLK_FREQ 0xc4 +/* I2CM Registers */ +#define I2CM_SM_SCL_CONFIG0 0xe0 +#define I2CM_FM_SCL_CONFIG0 0xe4 +#define I2CM_CONFIG0 0xe8 +#define I2CM_CONTROL0 0xec +#define I2CM_STATUS0 0xf0 +#define I2CM_INTERFACE_CONTROL0 0xf4 +#define I2CM_ADDR 0xff000 +#define I2CM_SLVADDR 0xfe0 +#define I2CM_WR_MASK 0x1e +#define I2CM_EXT_READ BIT(4) +#define I2CM_SHORT_READ BIT(3) +#define I2CM_FM_READ BIT(2) +#define I2CM_FM_WRITE BIT(1) +#define I2CM_FM_EN BIT(0) +#define I2CM_INTERFACE_CONTROL1 0xf8 +#define I2CM_SEG_PTR 0x7f80 +#define I2CM_SEG_ADDR 0x7f +#define I2CM_INTERFACE_WRDATA_0_3 0xfc +#define I2CM_INTERFACE_WRDATA_4_7 0x100 +#define I2CM_INTERFACE_WRDATA_8_11 0x104 +#define I2CM_INTERFACE_WRDATA_12_15 0x108 +#define I2CM_INTERFACE_RDDATA_0_3 0x10c +#define I2CM_INTERFACE_RDDATA_4_7 0x110 +#define I2CM_INTERFACE_RDDATA_8_11 0x114 +#define I2CM_INTERFACE_RDDATA_12_15 0x118 +/* SCDC Registers */ +#define SCDC_CONFIG0 0x140 +#define SCDC_I2C_FM_EN BIT(12) +#define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) +#define SCDC_UPD_FLAGS_POLL_EN BIT(4) +#define SCDC_CONTROL0 0x148 +#define SCDC_STATUS0 0x150 +#define STATUS_UPDATE BIT(0) +#define FRL_START BIT(4) +#define FLT_UPDATE BIT(5) +/* FLT Registers */ +#define FLT_CONFIG0 0x160 +#define FLT_CONFIG1 0x164 +#define FLT_CONFIG2 0x168 +#define FLT_CONTROL0 0x170 +/* Main Unit 2 Registers */ +#define MAINUNIT_STATUS0 0x180 +/* Video Interface Registers */ +#define VIDEO_INTERFACE_CONFIG0 0x800 +#define VIDEO_INTERFACE_CONFIG1 0x804 +#define VIDEO_INTERFACE_CONFIG2 0x808 +#define VIDEO_INTERFACE_CONTROL0 0x80c +#define VIDEO_INTERFACE_STATUS0 0x814 +/* Video Packing Registers */ +#define VIDEO_PACKING_CONFIG0 0x81c +/* Audio Interface Registers */ +#define AUDIO_INTERFACE_CONFIG0 0x820 +#define AUD_IF_SEL_MSK 0x3 +#define AUD_IF_SPDIF 0x2 +#define AUD_IF_I2S 0x1 +#define AUD_IF_PAI 0x0 +#define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) +#define AUD_FIFO_INIT_ON_OVF_EN BIT(2) +#define I2S_LINES_EN_MSK GENMASK(7, 4) +#define I2S_LINES_EN(x) BIT(x + 4) +#define I2S_BPCUV_RCV_MSK BIT(12) +#define I2S_BPCUV_RCV_EN BIT(12) +#define I2S_BPCUV_RCV_DIS 0 +#define SPDIF_LINES_EN GENMASK(19, 16) +#define AUD_FORMAT_MSK GENMASK(26, 24) +#define AUD_3DOBA (0x7 << 24) +#define AUD_3DASP (0x6 << 24) +#define AUD_MSOBA (0x5 << 24) +#define AUD_MSASP (0x4 << 24) +#define AUD_HBR (0x3 << 24) +#define AUD_DST (0x2 << 24) +#define AUD_OBA (0x1 << 24) +#define AUD_ASP (0x0 << 24) +#define AUDIO_INTERFACE_CONFIG1 0x824 +#define AUDIO_INTERFACE_CONTROL0 0x82c +#define AUDIO_FIFO_CLR_P BIT(0) +#define AUDIO_INTERFACE_STATUS0 0x834 +/* Frame Composer Registers */ +#define FRAME_COMPOSER_CONFIG0 0x840 +#define FRAME_COMPOSER_CONFIG1 0x844 +#define FRAME_COMPOSER_CONFIG2 0x848 +#define FRAME_COMPOSER_CONFIG3 0x84c +#define FRAME_COMPOSER_CONFIG4 0x850 +#define FRAME_COMPOSER_CONFIG5 0x854 +#define FRAME_COMPOSER_CONFIG6 0x858 +#define FRAME_COMPOSER_CONFIG7 0x85c +#define FRAME_COMPOSER_CONFIG8 0x860 +#define FRAME_COMPOSER_CONFIG9 0x864 +#define FRAME_COMPOSER_CONTROL0 0x86c +/* Video Monitor Registers */ +#define VIDEO_MONITOR_CONFIG0 0x880 +#define VIDEO_MONITOR_STATUS0 0x884 +#define VIDEO_MONITOR_STATUS1 0x888 +#define VIDEO_MONITOR_STATUS2 0x88c +#define VIDEO_MONITOR_STATUS3 0x890 +#define VIDEO_MONITOR_STATUS4 0x894 +#define VIDEO_MONITOR_STATUS5 0x898 +#define VIDEO_MONITOR_STATUS6 0x89c +/* HDCP2 Logic Registers */ +#define HDCP2LOGIC_CONFIG0 0x8e0 +#define HDCP2_BYPASS BIT(0) +#define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 +#define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 +/* HDCP14 Registers */ +#define HDCP14_CONFIG0 0x900 +#define HDCP14_CONFIG1 0x904 +#define HDCP14_CONFIG2 0x908 +#define HDCP14_CONFIG3 0x90c +#define HDCP14_KEY_SEED 0x914 +#define HDCP14_KEY_H 0x918 +#define HDCP14_KEY_L 0x91c +#define HDCP14_KEY_STATUS 0x920 +#define HDCP14_AKSV_H 0x924 +#define HDCP14_AKSV_L 0x928 +#define HDCP14_AN_H 0x92c +#define HDCP14_AN_L 0x930 +#define HDCP14_STATUS0 0x934 +#define HDCP14_STATUS1 0x938 +/* Scrambler Registers */ +#define SCRAMB_CONFIG0 0x960 +/* Video Configuration Registers */ +#define LINK_CONFIG0 0x968 +#define OPMODE_FRL_4LANES BIT(8) +#define OPMODE_DVI BIT(4) +#define OPMODE_FRL BIT(0) +/* TMDS FIFO Registers */ +#define TMDS_FIFO_CONFIG0 0x970 +#define TMDS_FIFO_CONTROL0 0x974 +/* FRL RSFEC Registers */ +#define FRL_RSFEC_CONFIG0 0xa20 +#define FRL_RSFEC_STATUS0 0xa30 +/* FRL Packetizer Registers */ +#define FRL_PKTZ_CONFIG0 0xa40 +#define FRL_PKTZ_CONTROL0 0xa44 +#define FRL_PKTZ_CONTROL1 0xa50 +#define FRL_PKTZ_STATUS1 0xa54 +/* Packet Scheduler Registers */ +#define PKTSCHED_CONFIG0 0xa80 +#define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 +#define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 +#define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c +#define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 +#define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 +#define PKTSCHED_PKT_CONFIG0 0xa98 +#define PKTSCHED_PKT_CONFIG1 0xa9c +#define PKTSCHED_DRMI_FIELDRATE BIT(13) +#define PKTSCHED_AVI_FIELDRATE BIT(12) +#define PKTSCHED_PKT_CONFIG2 0xaa0 +#define PKTSCHED_PKT_CONFIG3 0xaa4 +#define PKTSCHED_PKT_EN 0xaa8 +#define PKTSCHED_DRMI_TX_EN BIT(17) +#define PKTSCHED_AUDI_TX_EN BIT(15) +#define PKTSCHED_AVI_TX_EN BIT(13) +#define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) +#define PKTSCHED_AMD_TX_EN BIT(8) +#define PKTSCHED_GCP_TX_EN BIT(3) +#define PKTSCHED_AUDS_TX_EN BIT(2) +#define PKTSCHED_ACR_TX_EN BIT(1) +#define PKTSCHED_NULL_TX_EN BIT(0) +#define PKTSCHED_PKT_CONTROL0 0xaac +#define PKTSCHED_PKT_SEND 0xab0 +#define PKTSCHED_PKT_STATUS0 0xab4 +#define PKTSCHED_PKT_STATUS1 0xab8 +#define PKT_NULL_CONTENTS0 0xb00 +#define PKT_NULL_CONTENTS1 0xb04 +#define PKT_NULL_CONTENTS2 0xb08 +#define PKT_NULL_CONTENTS3 0xb0c +#define PKT_NULL_CONTENTS4 0xb10 +#define PKT_NULL_CONTENTS5 0xb14 +#define PKT_NULL_CONTENTS6 0xb18 +#define PKT_NULL_CONTENTS7 0xb1c +#define PKT_ACP_CONTENTS0 0xb20 +#define PKT_ACP_CONTENTS1 0xb24 +#define PKT_ACP_CONTENTS2 0xb28 +#define PKT_ACP_CONTENTS3 0xb2c +#define PKT_ACP_CONTENTS4 0xb30 +#define PKT_ACP_CONTENTS5 0xb34 +#define PKT_ACP_CONTENTS6 0xb38 +#define PKT_ACP_CONTENTS7 0xb3c +#define PKT_ISRC1_CONTENTS0 0xb40 +#define PKT_ISRC1_CONTENTS1 0xb44 +#define PKT_ISRC1_CONTENTS2 0xb48 +#define PKT_ISRC1_CONTENTS3 0xb4c +#define PKT_ISRC1_CONTENTS4 0xb50 +#define PKT_ISRC1_CONTENTS5 0xb54 +#define PKT_ISRC1_CONTENTS6 0xb58 +#define PKT_ISRC1_CONTENTS7 0xb5c +#define PKT_ISRC2_CONTENTS0 0xb60 +#define PKT_ISRC2_CONTENTS1 0xb64 +#define PKT_ISRC2_CONTENTS2 0xb68 +#define PKT_ISRC2_CONTENTS3 0xb6c +#define PKT_ISRC2_CONTENTS4 0xb70 +#define PKT_ISRC2_CONTENTS5 0xb74 +#define PKT_ISRC2_CONTENTS6 0xb78 +#define PKT_ISRC2_CONTENTS7 0xb7c +#define PKT_GMD_CONTENTS0 0xb80 +#define PKT_GMD_CONTENTS1 0xb84 +#define PKT_GMD_CONTENTS2 0xb88 +#define PKT_GMD_CONTENTS3 0xb8c +#define PKT_GMD_CONTENTS4 0xb90 +#define PKT_GMD_CONTENTS5 0xb94 +#define PKT_GMD_CONTENTS6 0xb98 +#define PKT_GMD_CONTENTS7 0xb9c +#define PKT_AMD_CONTENTS0 0xba0 +#define PKT_AMD_CONTENTS1 0xba4 +#define PKT_AMD_CONTENTS2 0xba8 +#define PKT_AMD_CONTENTS3 0xbac +#define PKT_AMD_CONTENTS4 0xbb0 +#define PKT_AMD_CONTENTS5 0xbb4 +#define PKT_AMD_CONTENTS6 0xbb8 +#define PKT_AMD_CONTENTS7 0xbbc +#define PKT_VSI_CONTENTS0 0xbc0 +#define PKT_VSI_CONTENTS1 0xbc4 +#define PKT_VSI_CONTENTS2 0xbc8 +#define PKT_VSI_CONTENTS3 0xbcc +#define PKT_VSI_CONTENTS4 0xbd0 +#define PKT_VSI_CONTENTS5 0xbd4 +#define PKT_VSI_CONTENTS6 0xbd8 +#define PKT_VSI_CONTENTS7 0xbdc +#define PKT_AVI_CONTENTS0 0xbe0 +#define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) +#define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 +#define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 +#define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 +#define PKT_AVI_CONTENTS1 0xbe4 +#define PKT_AVI_CONTENTS2 0xbe8 +#define PKT_AVI_CONTENTS3 0xbec +#define PKT_AVI_CONTENTS4 0xbf0 +#define PKT_AVI_CONTENTS5 0xbf4 +#define PKT_AVI_CONTENTS6 0xbf8 +#define PKT_AVI_CONTENTS7 0xbfc +#define PKT_SPDI_CONTENTS0 0xc00 +#define PKT_SPDI_CONTENTS1 0xc04 +#define PKT_SPDI_CONTENTS2 0xc08 +#define PKT_SPDI_CONTENTS3 0xc0c +#define PKT_SPDI_CONTENTS4 0xc10 +#define PKT_SPDI_CONTENTS5 0xc14 +#define PKT_SPDI_CONTENTS6 0xc18 +#define PKT_SPDI_CONTENTS7 0xc1c +#define PKT_AUDI_CONTENTS0 0xc20 +#define PKT_AUDI_CONTENTS1 0xc24 +#define PKT_AUDI_CONTENTS2 0xc28 +#define PKT_AUDI_CONTENTS3 0xc2c +#define PKT_AUDI_CONTENTS4 0xc30 +#define PKT_AUDI_CONTENTS5 0xc34 +#define PKT_AUDI_CONTENTS6 0xc38 +#define PKT_AUDI_CONTENTS7 0xc3c +#define PKT_NVI_CONTENTS0 0xc40 +#define PKT_NVI_CONTENTS1 0xc44 +#define PKT_NVI_CONTENTS2 0xc48 +#define PKT_NVI_CONTENTS3 0xc4c +#define PKT_NVI_CONTENTS4 0xc50 +#define PKT_NVI_CONTENTS5 0xc54 +#define PKT_NVI_CONTENTS6 0xc58 +#define PKT_NVI_CONTENTS7 0xc5c +#define PKT_DRMI_CONTENTS0 0xc60 +#define PKT_DRMI_CONTENTS1 0xc64 +#define PKT_DRMI_CONTENTS2 0xc68 +#define PKT_DRMI_CONTENTS3 0xc6c +#define PKT_DRMI_CONTENTS4 0xc70 +#define PKT_DRMI_CONTENTS5 0xc74 +#define PKT_DRMI_CONTENTS6 0xc78 +#define PKT_DRMI_CONTENTS7 0xc7c +#define PKT_GHDMI1_CONTENTS0 0xc80 +#define PKT_GHDMI1_CONTENTS1 0xc84 +#define PKT_GHDMI1_CONTENTS2 0xc88 +#define PKT_GHDMI1_CONTENTS3 0xc8c +#define PKT_GHDMI1_CONTENTS4 0xc90 +#define PKT_GHDMI1_CONTENTS5 0xc94 +#define PKT_GHDMI1_CONTENTS6 0xc98 +#define PKT_GHDMI1_CONTENTS7 0xc9c +#define PKT_GHDMI2_CONTENTS0 0xca0 +#define PKT_GHDMI2_CONTENTS1 0xca4 +#define PKT_GHDMI2_CONTENTS2 0xca8 +#define PKT_GHDMI2_CONTENTS3 0xcac +#define PKT_GHDMI2_CONTENTS4 0xcb0 +#define PKT_GHDMI2_CONTENTS5 0xcb4 +#define PKT_GHDMI2_CONTENTS6 0xcb8 +#define PKT_GHDMI2_CONTENTS7 0xcbc +/* EMP Packetizer Registers */ +#define PKT_EMP_CONFIG0 0xce0 +#define PKT_EMP_CONTROL0 0xcec +#define PKT_EMP_CONTROL1 0xcf0 +#define PKT_EMP_CONTROL2 0xcf4 +#define PKT_EMP_VTEM_CONTENTS0 0xd00 +#define PKT_EMP_VTEM_CONTENTS1 0xd04 +#define PKT_EMP_VTEM_CONTENTS2 0xd08 +#define PKT_EMP_VTEM_CONTENTS3 0xd0c +#define PKT_EMP_VTEM_CONTENTS4 0xd10 +#define PKT_EMP_VTEM_CONTENTS5 0xd14 +#define PKT_EMP_VTEM_CONTENTS6 0xd18 +#define PKT_EMP_VTEM_CONTENTS7 0xd1c +#define PKT0_EMP_CVTEM_CONTENTS0 0xd20 +#define PKT0_EMP_CVTEM_CONTENTS1 0xd24 +#define PKT0_EMP_CVTEM_CONTENTS2 0xd28 +#define PKT0_EMP_CVTEM_CONTENTS3 0xd2c +#define PKT0_EMP_CVTEM_CONTENTS4 0xd30 +#define PKT0_EMP_CVTEM_CONTENTS5 0xd34 +#define PKT0_EMP_CVTEM_CONTENTS6 0xd38 +#define PKT0_EMP_CVTEM_CONTENTS7 0xd3c +#define PKT1_EMP_CVTEM_CONTENTS0 0xd40 +#define PKT1_EMP_CVTEM_CONTENTS1 0xd44 +#define PKT1_EMP_CVTEM_CONTENTS2 0xd48 +#define PKT1_EMP_CVTEM_CONTENTS3 0xd4c +#define PKT1_EMP_CVTEM_CONTENTS4 0xd50 +#define PKT1_EMP_CVTEM_CONTENTS5 0xd54 +#define PKT1_EMP_CVTEM_CONTENTS6 0xd58 +#define PKT1_EMP_CVTEM_CONTENTS7 0xd5c +#define PKT2_EMP_CVTEM_CONTENTS0 0xd60 +#define PKT2_EMP_CVTEM_CONTENTS1 0xd64 +#define PKT2_EMP_CVTEM_CONTENTS2 0xd68 +#define PKT2_EMP_CVTEM_CONTENTS3 0xd6c +#define PKT2_EMP_CVTEM_CONTENTS4 0xd70 +#define PKT2_EMP_CVTEM_CONTENTS5 0xd74 +#define PKT2_EMP_CVTEM_CONTENTS6 0xd78 +#define PKT2_EMP_CVTEM_CONTENTS7 0xd7c +#define PKT3_EMP_CVTEM_CONTENTS0 0xd80 +#define PKT3_EMP_CVTEM_CONTENTS1 0xd84 +#define PKT3_EMP_CVTEM_CONTENTS2 0xd88 +#define PKT3_EMP_CVTEM_CONTENTS3 0xd8c +#define PKT3_EMP_CVTEM_CONTENTS4 0xd90 +#define PKT3_EMP_CVTEM_CONTENTS5 0xd94 +#define PKT3_EMP_CVTEM_CONTENTS6 0xd98 +#define PKT3_EMP_CVTEM_CONTENTS7 0xd9c +#define PKT4_EMP_CVTEM_CONTENTS0 0xda0 +#define PKT4_EMP_CVTEM_CONTENTS1 0xda4 +#define PKT4_EMP_CVTEM_CONTENTS2 0xda8 +#define PKT4_EMP_CVTEM_CONTENTS3 0xdac +#define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 +#define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 +#define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 +#define PKT4_EMP_CVTEM_CONTENTS7 0xdbc +#define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 +#define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 +#define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 +#define PKT5_EMP_CVTEM_CONTENTS3 0xdcc +#define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 +#define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 +#define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 +#define PKT5_EMP_CVTEM_CONTENTS7 0xddc +/* Audio Packetizer Registers */ +#define AUDPKT_CONTROL0 0xe20 +#define AUDPKT_PBIT_FORCE_EN_MASK BIT(12) +#define AUDPKT_PBIT_FORCE_EN BIT(12) +#define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) +#define AUDPKT_CHSTATUS_OVR_EN BIT(0) +#define AUDPKT_CONTROL1 0xe24 +#define AUDPKT_ACR_CONTROL0 0xe40 +#define AUDPKT_ACR_N_VALUE 0xfffff +#define AUDPKT_ACR_CONTROL1 0xe44 +#define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) +#define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) +#define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) +#define AUDPKT_ACR_CTS_OVR_EN BIT(1) +#define AUDPKT_ACR_STATUS0 0xe4c +#define AUDPKT_CHSTATUS_OVR0 0xe60 +#define AUDPKT_CHSTATUS_OVR1 0xe64 +/* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ +#define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) +#define AUDPKT_CHSTATUS_SR_22050 0x4 +#define AUDPKT_CHSTATUS_SR_24000 0x6 +#define AUDPKT_CHSTATUS_SR_32000 0x3 +#define AUDPKT_CHSTATUS_SR_44100 0x0 +#define AUDPKT_CHSTATUS_SR_48000 0x2 +#define AUDPKT_CHSTATUS_SR_88200 0x8 +#define AUDPKT_CHSTATUS_SR_96000 0xa +#define AUDPKT_CHSTATUS_SR_176400 0xc +#define AUDPKT_CHSTATUS_SR_192000 0xe +#define AUDPKT_CHSTATUS_SR_768000 0x9 +#define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 +/* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ +#define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) +#define AUDPKT_CHSTATUS_OSR_8000 0x6 +#define AUDPKT_CHSTATUS_OSR_11025 0xa +#define AUDPKT_CHSTATUS_OSR_12000 0x2 +#define AUDPKT_CHSTATUS_OSR_16000 0x8 +#define AUDPKT_CHSTATUS_OSR_22050 0xb +#define AUDPKT_CHSTATUS_OSR_24000 0x9 +#define AUDPKT_CHSTATUS_OSR_32000 0xc +#define AUDPKT_CHSTATUS_OSR_44100 0xf +#define AUDPKT_CHSTATUS_OSR_48000 0xd +#define AUDPKT_CHSTATUS_OSR_88200 0x7 +#define AUDPKT_CHSTATUS_OSR_96000 0x5 +#define AUDPKT_CHSTATUS_OSR_176400 0x3 +#define AUDPKT_CHSTATUS_OSR_192000 0x1 +#define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 +#define AUDPKT_CHSTATUS_OVR2 0xe68 +#define AUDPKT_CHSTATUS_OVR3 0xe6c +#define AUDPKT_CHSTATUS_OVR4 0xe70 +#define AUDPKT_CHSTATUS_OVR5 0xe74 +#define AUDPKT_CHSTATUS_OVR6 0xe78 +#define AUDPKT_CHSTATUS_OVR7 0xe7c +#define AUDPKT_CHSTATUS_OVR8 0xe80 +#define AUDPKT_CHSTATUS_OVR9 0xe84 +#define AUDPKT_CHSTATUS_OVR10 0xe88 +#define AUDPKT_CHSTATUS_OVR11 0xe8c +#define AUDPKT_CHSTATUS_OVR12 0xe90 +#define AUDPKT_CHSTATUS_OVR13 0xe94 +#define AUDPKT_CHSTATUS_OVR14 0xe98 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac +#define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec +#define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c +#define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c +#define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 +#define AUDPKT_VBIT_OVR0 0xf24 +/* CEC Registers */ +#define CEC_TX_CONTROL 0x1000 +#define CEC_STATUS 0x1004 +#define CEC_CONFIG 0x1008 +#define CEC_ADDR 0x100c +#define CEC_TX_COUNT 0x1020 +#define CEC_TX_DATA3_0 0x1024 +#define CEC_TX_DATA7_4 0x1028 +#define CEC_TX_DATA11_8 0x102c +#define CEC_TX_DATA15_12 0x1030 +#define CEC_RX_COUNT_STATUS 0x1040 +#define CEC_RX_DATA3_0 0x1044 +#define CEC_RX_DATA7_4 0x1048 +#define CEC_RX_DATA11_8 0x104c +#define CEC_RX_DATA15_12 0x1050 +#define CEC_LOCK_CONTROL 0x1054 +#define CEC_RXQUAL_BITTIME_CONFIG 0x1060 +#define CEC_RX_BITTIME_CONFIG 0x1064 +#define CEC_TX_BITTIME_CONFIG 0x1068 +/* eARC RX CMDC Registers */ +#define EARCRX_CMDC_CONFIG0 0x1800 +#define EARCRX_XACTREAD_STOP_CFG BIT(26) +#define EARCRX_XACTREAD_RETRY_CFG BIT(25) +#define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) +#define EARCRX_CMDC_XACT_RESTART_EN BIT(18) +#define EARCRX_CMDC_CONFIG1 0x1804 +#define EARCRX_CMDC_CONTROL 0x1808 +#define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) +#define EARCRX_CMDC_DISCOVERY_EN BIT(3) +#define EARCRX_CONNECTOR_HPD BIT(1) +#define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c +#define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 +#define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 +#define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 +#define EARCRX_CMDC_STATUS 0x181c +#define EARCRX_CMDC_XACT_INFO 0x1820 +#define EARCRX_CMDC_XACT_ACTION 0x1824 +#define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 +#define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c +#define EARCRX_CMDC_XACT_WR0 0x1840 +#define EARCRX_CMDC_XACT_WR1 0x1844 +#define EARCRX_CMDC_XACT_WR2 0x1848 +#define EARCRX_CMDC_XACT_WR3 0x184c +#define EARCRX_CMDC_XACT_WR4 0x1850 +#define EARCRX_CMDC_XACT_WR5 0x1854 +#define EARCRX_CMDC_XACT_WR6 0x1858 +#define EARCRX_CMDC_XACT_WR7 0x185c +#define EARCRX_CMDC_XACT_WR8 0x1860 +#define EARCRX_CMDC_XACT_WR9 0x1864 +#define EARCRX_CMDC_XACT_WR10 0x1868 +#define EARCRX_CMDC_XACT_WR11 0x186c +#define EARCRX_CMDC_XACT_WR12 0x1870 +#define EARCRX_CMDC_XACT_WR13 0x1874 +#define EARCRX_CMDC_XACT_WR14 0x1878 +#define EARCRX_CMDC_XACT_WR15 0x187c +#define EARCRX_CMDC_XACT_WR16 0x1880 +#define EARCRX_CMDC_XACT_WR17 0x1884 +#define EARCRX_CMDC_XACT_WR18 0x1888 +#define EARCRX_CMDC_XACT_WR19 0x188c +#define EARCRX_CMDC_XACT_WR20 0x1890 +#define EARCRX_CMDC_XACT_WR21 0x1894 +#define EARCRX_CMDC_XACT_WR22 0x1898 +#define EARCRX_CMDC_XACT_WR23 0x189c +#define EARCRX_CMDC_XACT_WR24 0x18a0 +#define EARCRX_CMDC_XACT_WR25 0x18a4 +#define EARCRX_CMDC_XACT_WR26 0x18a8 +#define EARCRX_CMDC_XACT_WR27 0x18ac +#define EARCRX_CMDC_XACT_WR28 0x18b0 +#define EARCRX_CMDC_XACT_WR29 0x18b4 +#define EARCRX_CMDC_XACT_WR30 0x18b8 +#define EARCRX_CMDC_XACT_WR31 0x18bc +#define EARCRX_CMDC_XACT_WR32 0x18c0 +#define EARCRX_CMDC_XACT_WR33 0x18c4 +#define EARCRX_CMDC_XACT_WR34 0x18c8 +#define EARCRX_CMDC_XACT_WR35 0x18cc +#define EARCRX_CMDC_XACT_WR36 0x18d0 +#define EARCRX_CMDC_XACT_WR37 0x18d4 +#define EARCRX_CMDC_XACT_WR38 0x18d8 +#define EARCRX_CMDC_XACT_WR39 0x18dc +#define EARCRX_CMDC_XACT_WR40 0x18e0 +#define EARCRX_CMDC_XACT_WR41 0x18e4 +#define EARCRX_CMDC_XACT_WR42 0x18e8 +#define EARCRX_CMDC_XACT_WR43 0x18ec +#define EARCRX_CMDC_XACT_WR44 0x18f0 +#define EARCRX_CMDC_XACT_WR45 0x18f4 +#define EARCRX_CMDC_XACT_WR46 0x18f8 +#define EARCRX_CMDC_XACT_WR47 0x18fc +#define EARCRX_CMDC_XACT_WR48 0x1900 +#define EARCRX_CMDC_XACT_WR49 0x1904 +#define EARCRX_CMDC_XACT_WR50 0x1908 +#define EARCRX_CMDC_XACT_WR51 0x190c +#define EARCRX_CMDC_XACT_WR52 0x1910 +#define EARCRX_CMDC_XACT_WR53 0x1914 +#define EARCRX_CMDC_XACT_WR54 0x1918 +#define EARCRX_CMDC_XACT_WR55 0x191c +#define EARCRX_CMDC_XACT_WR56 0x1920 +#define EARCRX_CMDC_XACT_WR57 0x1924 +#define EARCRX_CMDC_XACT_WR58 0x1928 +#define EARCRX_CMDC_XACT_WR59 0x192c +#define EARCRX_CMDC_XACT_WR60 0x1930 +#define EARCRX_CMDC_XACT_WR61 0x1934 +#define EARCRX_CMDC_XACT_WR62 0x1938 +#define EARCRX_CMDC_XACT_WR63 0x193c +#define EARCRX_CMDC_XACT_WR64 0x1940 +#define EARCRX_CMDC_XACT_RD0 0x1960 +#define EARCRX_CMDC_XACT_RD1 0x1964 +#define EARCRX_CMDC_XACT_RD2 0x1968 +#define EARCRX_CMDC_XACT_RD3 0x196c +#define EARCRX_CMDC_XACT_RD4 0x1970 +#define EARCRX_CMDC_XACT_RD5 0x1974 +#define EARCRX_CMDC_XACT_RD6 0x1978 +#define EARCRX_CMDC_XACT_RD7 0x197c +#define EARCRX_CMDC_XACT_RD8 0x1980 +#define EARCRX_CMDC_XACT_RD9 0x1984 +#define EARCRX_CMDC_XACT_RD10 0x1988 +#define EARCRX_CMDC_XACT_RD11 0x198c +#define EARCRX_CMDC_XACT_RD12 0x1990 +#define EARCRX_CMDC_XACT_RD13 0x1994 +#define EARCRX_CMDC_XACT_RD14 0x1998 +#define EARCRX_CMDC_XACT_RD15 0x199c +#define EARCRX_CMDC_XACT_RD16 0x19a0 +#define EARCRX_CMDC_XACT_RD17 0x19a4 +#define EARCRX_CMDC_XACT_RD18 0x19a8 +#define EARCRX_CMDC_XACT_RD19 0x19ac +#define EARCRX_CMDC_XACT_RD20 0x19b0 +#define EARCRX_CMDC_XACT_RD21 0x19b4 +#define EARCRX_CMDC_XACT_RD22 0x19b8 +#define EARCRX_CMDC_XACT_RD23 0x19bc +#define EARCRX_CMDC_XACT_RD24 0x19c0 +#define EARCRX_CMDC_XACT_RD25 0x19c4 +#define EARCRX_CMDC_XACT_RD26 0x19c8 +#define EARCRX_CMDC_XACT_RD27 0x19cc +#define EARCRX_CMDC_XACT_RD28 0x19d0 +#define EARCRX_CMDC_XACT_RD29 0x19d4 +#define EARCRX_CMDC_XACT_RD30 0x19d8 +#define EARCRX_CMDC_XACT_RD31 0x19dc +#define EARCRX_CMDC_XACT_RD32 0x19e0 +#define EARCRX_CMDC_XACT_RD33 0x19e4 +#define EARCRX_CMDC_XACT_RD34 0x19e8 +#define EARCRX_CMDC_XACT_RD35 0x19ec +#define EARCRX_CMDC_XACT_RD36 0x19f0 +#define EARCRX_CMDC_XACT_RD37 0x19f4 +#define EARCRX_CMDC_XACT_RD38 0x19f8 +#define EARCRX_CMDC_XACT_RD39 0x19fc +#define EARCRX_CMDC_XACT_RD40 0x1a00 +#define EARCRX_CMDC_XACT_RD41 0x1a04 +#define EARCRX_CMDC_XACT_RD42 0x1a08 +#define EARCRX_CMDC_XACT_RD43 0x1a0c +#define EARCRX_CMDC_XACT_RD44 0x1a10 +#define EARCRX_CMDC_XACT_RD45 0x1a14 +#define EARCRX_CMDC_XACT_RD46 0x1a18 +#define EARCRX_CMDC_XACT_RD47 0x1a1c +#define EARCRX_CMDC_XACT_RD48 0x1a20 +#define EARCRX_CMDC_XACT_RD49 0x1a24 +#define EARCRX_CMDC_XACT_RD50 0x1a28 +#define EARCRX_CMDC_XACT_RD51 0x1a2c +#define EARCRX_CMDC_XACT_RD52 0x1a30 +#define EARCRX_CMDC_XACT_RD53 0x1a34 +#define EARCRX_CMDC_XACT_RD54 0x1a38 +#define EARCRX_CMDC_XACT_RD55 0x1a3c +#define EARCRX_CMDC_XACT_RD56 0x1a40 +#define EARCRX_CMDC_XACT_RD57 0x1a44 +#define EARCRX_CMDC_XACT_RD58 0x1a48 +#define EARCRX_CMDC_XACT_RD59 0x1a4c +#define EARCRX_CMDC_XACT_RD60 0x1a50 +#define EARCRX_CMDC_XACT_RD61 0x1a54 +#define EARCRX_CMDC_XACT_RD62 0x1a58 +#define EARCRX_CMDC_XACT_RD63 0x1a5c +#define EARCRX_CMDC_XACT_RD64 0x1a60 +#define EARCRX_CMDC_SYNC_CONFIG 0x1b00 +/* eARC RX DMAC Registers */ +#define EARCRX_DMAC_PHY_CONTROL 0x1c00 +#define EARCRX_DMAC_CONFIG 0x1c08 +#define EARCRX_DMAC_CONTROL0 0x1c0c +#define EARCRX_DMAC_AUDIO_EN BIT(1) +#define EARCRX_DMAC_EN BIT(0) +#define EARCRX_DMAC_CONTROL1 0x1c10 +#define EARCRX_DMAC_STATUS 0x1c14 +#define EARCRX_DMAC_CHSTATUS0 0x1c18 +#define EARCRX_DMAC_CHSTATUS1 0x1c1c +#define EARCRX_DMAC_CHSTATUS2 0x1c20 +#define EARCRX_DMAC_CHSTATUS3 0x1c24 +#define EARCRX_DMAC_CHSTATUS4 0x1c28 +#define EARCRX_DMAC_CHSTATUS5 0x1c2c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec +#define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 +#define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 +#define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 +#define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c +#define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 +#define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 +#define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 +#define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c +#define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 +#define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 +#define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 +#define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c +#define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 +#define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 +#define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 +#define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c +#define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 +/* Main Unit Interrupt Registers */ +#define MAIN_INTVEC_INDEX 0x3000 +#define MAINUNIT_0_INT_STATUS 0x3010 +#define MAINUNIT_0_INT_MASK_N 0x3014 +#define MAINUNIT_0_INT_CLEAR 0x3018 +#define MAINUNIT_0_INT_FORCE 0x301c +#define MAINUNIT_1_INT_STATUS 0x3020 +#define FLT_EXIT_TO_LTSL_IRQ BIT(22) +#define FLT_EXIT_TO_LTS4_IRQ BIT(21) +#define FLT_EXIT_TO_LTSP_IRQ BIT(20) +#define SCDC_NACK_RCVD_IRQ BIT(12) +#define SCDC_RR_REPLY_STOP_IRQ BIT(11) +#define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) +#define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) +#define SCDC_UPD_FLAGS_RD_IRQ BIT(8) +#define I2CM_NACK_RCVD_IRQ BIT(2) +#define I2CM_READ_REQUEST_IRQ BIT(1) +#define I2CM_OP_DONE_IRQ BIT(0) +#define MAINUNIT_1_INT_MASK_N 0x3024 +#define I2CM_NACK_RCVD_MASK_N BIT(2) +#define I2CM_READ_REQUEST_MASK_N BIT(1) +#define I2CM_OP_DONE_MASK_N BIT(0) +#define MAINUNIT_1_INT_CLEAR 0x3028 +#define I2CM_NACK_RCVD_CLEAR BIT(2) +#define I2CM_READ_REQUEST_CLEAR BIT(1) +#define I2CM_OP_DONE_CLEAR BIT(0) +#define MAINUNIT_1_INT_FORCE 0x302c +/* AVPUNIT Interrupt Registers */ +#define AVP_INTVEC_INDEX 0x3800 +#define AVP_0_INT_STATUS 0x3810 +#define AVP_0_INT_MASK_N 0x3814 +#define AVP_0_INT_CLEAR 0x3818 +#define AVP_0_INT_FORCE 0x381c +#define AVP_1_INT_STATUS 0x3820 +#define AVP_1_INT_MASK_N 0x3824 +#define HDCP14_AUTH_CHG_MASK_N BIT(6) +#define AVP_1_INT_CLEAR 0x3828 +#define AVP_1_INT_FORCE 0x382c +#define AVP_2_INT_STATUS 0x3830 +#define AVP_2_INT_MASK_N 0x3834 +#define AVP_2_INT_CLEAR 0x3838 +#define AVP_2_INT_FORCE 0x383c +#define AVP_3_INT_STATUS 0x3840 +#define AVP_3_INT_MASK_N 0x3844 +#define AVP_3_INT_CLEAR 0x3848 +#define AVP_3_INT_FORCE 0x384c +#define AVP_4_INT_STATUS 0x3850 +#define AVP_4_INT_MASK_N 0x3854 +#define AVP_4_INT_CLEAR 0x3858 +#define AVP_4_INT_FORCE 0x385c +#define AVP_5_INT_STATUS 0x3860 +#define AVP_5_INT_MASK_N 0x3864 +#define AVP_5_INT_CLEAR 0x3868 +#define AVP_5_INT_FORCE 0x386c +#define AVP_6_INT_STATUS 0x3870 +#define AVP_6_INT_MASK_N 0x3874 +#define AVP_6_INT_CLEAR 0x3878 +#define AVP_6_INT_FORCE 0x387c +/* CEC Interrupt Registers */ +#define CEC_INT_STATUS 0x4000 +#define CEC_INT_MASK_N 0x4004 +#define CEC_INT_CLEAR 0x4008 +#define CEC_INT_FORCE 0x400c +/* eARC RX Interrupt Registers */ +#define EARCRX_INTVEC_INDEX 0x4800 +#define EARCRX_0_INT_STATUS 0x4810 +#define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) +#define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) +#define EARCRX_0_INT_MASK_N 0x4814 +#define EARCRX_0_INT_CLEAR 0x4818 +#define EARCRX_0_INT_FORCE 0x481c +#define EARCRX_1_INT_STATUS 0x4820 +#define EARCRX_1_INT_MASK_N 0x4824 +#define EARCRX_1_INT_CLEAR 0x4828 +#define EARCRX_1_INT_FORCE 0x482c + +#endif /* __DW_HDMI_QP_H__ */ diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index aca5bb0866f8..b2338e567290 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -162,6 +162,8 @@ struct dw_hdmi { void __iomem *regs; bool sink_is_hdmi; bool sink_has_audio; + bool support_hdmi; + int force_output; struct pinctrl *pinctrl; struct pinctrl_state *default_state; @@ -254,6 +256,25 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, hdmi_modb(hdmi, data << shift, mask, reg); } +static bool dw_hdmi_check_output_type_changed(struct dw_hdmi *hdmi) +{ + bool sink_hdmi; + + sink_hdmi = hdmi->sink_is_hdmi; + + if (hdmi->force_output == 1) + hdmi->sink_is_hdmi = true; + else if (hdmi->force_output == 2) + hdmi->sink_is_hdmi = false; + else + hdmi->sink_is_hdmi = hdmi->support_hdmi; + + if (sink_hdmi != hdmi->sink_is_hdmi) + return true; + + return false; +} + static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) { hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, @@ -2531,6 +2552,45 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, return 0; } +void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi) +{ + if (!hdmi->bridge_is_on) + return; + + hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); + dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); + hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP); +} +EXPORT_SYMBOL_GPL(dw_hdmi_set_quant_range); + +void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val) +{ + hdmi->force_output = val; + + if (!dw_hdmi_check_output_type_changed(hdmi)) + return; + + if (!hdmi->bridge_is_on) + return; + + hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP); + dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); + hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP); +} +EXPORT_SYMBOL_GPL(dw_hdmi_set_output_type); + +bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi) +{ + return hdmi->sink_is_hdmi; +} +EXPORT_SYMBOL_GPL(dw_hdmi_get_output_whether_hdmi); + +int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi) +{ + return hdmi->support_hdmi; +} +EXPORT_SYMBOL_GPL(dw_hdmi_get_output_type_cap); + static void dw_hdmi_connector_force(struct drm_connector *connector) { struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, @@ -3682,6 +3742,35 @@ void dw_hdmi_unbind(struct dw_hdmi *hdmi) } EXPORT_SYMBOL_GPL(dw_hdmi_unbind); +void dw_hdmi_suspend(struct dw_hdmi *hdmi) +{ + if (!hdmi) + return; + + mutex_lock(&hdmi->mutex); + + /* + * When system shutdown, hdmi should be disabled. + * When system suspend, dw_hdmi_bridge_disable will disable hdmi first. + * To prevent duplicate operation, we should determine whether hdmi + * has been disabled. + */ + if (!hdmi->disabled) { + hdmi->disabled = true; + dw_hdmi_update_power(hdmi); + dw_hdmi_update_phy_mask(hdmi); + } + mutex_unlock(&hdmi->mutex); + + //[CC: needed?] + // if (hdmi->irq) + // disable_irq(hdmi->irq); + // cancel_delayed_work(&hdmi->work); + // flush_workqueue(hdmi->workqueue); + pinctrl_pm_select_sleep_state(hdmi->dev); +} +EXPORT_SYMBOL_GPL(dw_hdmi_suspend); + void dw_hdmi_resume(struct dw_hdmi *hdmi) { dw_hdmi_init_hw(hdmi); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index af43a0414b78..8ebdec7254f2 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -851,6 +851,10 @@ enum { HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, +/* HDMI_FC_GCP */ + HDMI_FC_GCP_SET_AVMUTE = 0x2, + HDMI_FC_GCP_CLEAR_AVMUTE = 0x1, + /* FC_DBGFORCE field values */ HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index fe33092abbe7..a5d1a70d9b98 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -4,21 +4,32 @@ */ #include +#include +#include #include #include #include #include +#include #include #include +#include +#include +#include +#include #include #include #include #include #include +#include + #include "rockchip_drm_drv.h" +#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) + #define RK3228_GRF_SOC_CON2 0x0408 #define RK3228_HDMI_SDAIN_MSK BIT(14) #define RK3228_HDMI_SCLIN_MSK BIT(13) @@ -29,8 +40,11 @@ #define RK3288_GRF_SOC_CON6 0x025C #define RK3288_HDMI_LCDC_SEL BIT(4) -#define RK3328_GRF_SOC_CON2 0x0408 +#define RK3288_GRF_SOC_CON16 0x03a8 +#define RK3288_HDMI_LCDC0_YUV420 BIT(2) +#define RK3288_HDMI_LCDC1_YUV420 BIT(3) +#define RK3328_GRF_SOC_CON2 0x0408 #define RK3328_HDMI_SDAIN_MSK BIT(11) #define RK3328_HDMI_SCLIN_MSK BIT(10) #define RK3328_HDMI_HPD_IOE BIT(2) @@ -54,32 +68,177 @@ #define RK3568_HDMI_SDAIN_MSK BIT(15) #define RK3568_HDMI_SCLIN_MSK BIT(14) -#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) +#define RK3588_GRF_SOC_CON2 0x0308 +#define RK3588_HDMI1_HPD_INT_MSK BIT(15) +#define RK3588_HDMI1_HPD_INT_CLR BIT(14) +#define RK3588_HDMI0_HPD_INT_MSK BIT(13) +#define RK3588_HDMI0_HPD_INT_CLR BIT(12) +#define RK3588_GRF_SOC_CON7 0x031c +#define RK3588_SET_HPD_PATH_MASK (0x3 << 12) +#define RK3588_GRF_SOC_STATUS1 0x0384 +#define RK3588_HDMI0_LOW_MORETHAN100MS BIT(20) +#define RK3588_HDMI0_HPD_PORT_LEVEL BIT(19) +#define RK3588_HDMI0_IHPD_PORT BIT(18) +#define RK3588_HDMI0_OHPD_INT BIT(17) +#define RK3588_HDMI0_LEVEL_INT BIT(16) +#define RK3588_HDMI0_INTR_CHANGE_CNT (0x7 << 13) +#define RK3588_HDMI1_LOW_MORETHAN100MS BIT(28) +#define RK3588_HDMI1_HPD_PORT_LEVEL BIT(27) +#define RK3588_HDMI1_IHPD_PORT BIT(26) +#define RK3588_HDMI1_OHPD_INT BIT(25) +#define RK3588_HDMI1_LEVEL_INT BIT(24) +#define RK3588_HDMI1_INTR_CHANGE_CNT (0x7 << 21) + +#define RK3588_GRF_VO1_CON3 0x000c +#define RK3588_COLOR_FORMAT_MASK 0xf +#define RK3588_YUV444 0x2 +#define RK3588_YUV420 0x3 +#define RK3588_COMPRESSED_DATA 0xb +#define RK3588_COLOR_DEPTH_MASK (0xf << 4) +#define RK3588_8BPC (0x5 << 4) +#define RK3588_10BPC (0x6 << 4) +#define RK3588_CECIN_MASK BIT(8) +#define RK3588_SCLIN_MASK BIT(9) +#define RK3588_SDAIN_MASK BIT(10) +#define RK3588_MODE_MASK BIT(11) +#define RK3588_COMPRESS_MODE_MASK BIT(12) +#define RK3588_I2S_SEL_MASK BIT(13) +#define RK3588_SPDIF_SEL_MASK BIT(14) +#define RK3588_GRF_VO1_CON4 0x0010 +#define RK3588_HDMI21_MASK BIT(0) +#define RK3588_GRF_VO1_CON9 0x0024 +#define RK3588_HDMI0_GRANT_SEL BIT(10) +#define RK3588_HDMI0_GRANT_SW BIT(11) +#define RK3588_HDMI1_GRANT_SEL BIT(12) +#define RK3588_HDMI1_GRANT_SW BIT(13) +#define RK3588_GRF_VO1_CON6 0x0018 +#define RK3588_GRF_VO1_CON7 0x001c + +#define COLOR_DEPTH_10BIT BIT(31) +#define HDMI_FRL_MODE BIT(30) +#define HDMI_EARC_MODE BIT(29) + +#define HDMI20_MAX_RATE 600000 +#define HDMI_8K60_RATE 2376000 /** * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips * @lcdsel_grf_reg: grf register offset of lcdc select + * @ddc_en_reg: grf register offset of hdmi ddc enable * @lcdsel_big: reg value of selecting vop big for HDMI * @lcdsel_lit: reg value of selecting vop little for HDMI + * @split_mode: flag indicating split mode capability */ struct rockchip_hdmi_chip_data { int lcdsel_grf_reg; + int ddc_en_reg; u32 lcdsel_big; u32 lcdsel_lit; + bool split_mode; +}; + +enum hdmi_frl_rate_per_lane { + FRL_12G_PER_LANE = 12, + FRL_10G_PER_LANE = 10, + FRL_8G_PER_LANE = 8, + FRL_6G_PER_LANE = 6, + FRL_3G_PER_LANE = 3, +}; + +enum rk_if_color_depth { + RK_IF_DEPTH_8, + RK_IF_DEPTH_10, + RK_IF_DEPTH_12, + RK_IF_DEPTH_16, + RK_IF_DEPTH_420_10, + RK_IF_DEPTH_420_12, + RK_IF_DEPTH_420_16, + RK_IF_DEPTH_6, + RK_IF_DEPTH_MAX, +}; + +enum rk_if_color_format { + RK_IF_FORMAT_RGB, /* default RGB */ + RK_IF_FORMAT_YCBCR444, /* YCBCR 444 */ + RK_IF_FORMAT_YCBCR422, /* YCBCR 422 */ + RK_IF_FORMAT_YCBCR420, /* YCBCR 420 */ + RK_IF_FORMAT_YCBCR_HQ, /* Highest subsampled YUV */ + RK_IF_FORMAT_YCBCR_LQ, /* Lowest subsampled YUV */ + RK_IF_FORMAT_MAX, }; struct rockchip_hdmi { struct device *dev; struct regmap *regmap; + struct regmap *vo1_regmap; struct rockchip_encoder encoder; + struct drm_device *drm_dev; const struct rockchip_hdmi_chip_data *chip_data; - const struct dw_hdmi_plat_data *plat_data; + struct dw_hdmi_plat_data *plat_data; + struct clk *aud_clk; struct clk *ref_clk; struct clk *grf_clk; + struct clk *hclk_vio; + struct clk *hclk_vo1; + struct clk *hclk_vop; + struct clk *hpd_clk; + struct clk *pclk; + struct clk *earc_clk; + struct clk *hdmitx_ref; struct dw_hdmi *hdmi; + struct dw_hdmi_qp *hdmi_qp; + struct regulator *avdd_0v9; struct regulator *avdd_1v8; struct phy *phy; + + u32 max_tmdsclk; + bool unsupported_yuv_input; + bool unsupported_deep_color; + bool skip_check_420_mode; + u8 force_output; + u8 id; + bool hpd_stat; + bool is_hdmi_qp; + bool user_split_mode; + + unsigned long bus_format; + unsigned long output_bus_format; + unsigned long enc_out_encoding; + int color_changed; + int hpd_irq; + int vp_id; + + struct drm_property *color_depth_property; + struct drm_property *hdmi_output_property; + struct drm_property *colordepth_capacity; + struct drm_property *outputmode_capacity; + struct drm_property *quant_range; + struct drm_property *hdr_panel_metadata_property; + struct drm_property *next_hdr_sink_data_property; + struct drm_property *output_hdmi_dvi; + struct drm_property *output_type_capacity; + struct drm_property *user_split_mode_prop; + + struct drm_property_blob *hdr_panel_blob_ptr; + struct drm_property_blob *next_hdr_data_ptr; + + unsigned int colordepth; + unsigned int colorimetry; + unsigned int hdmi_quant_range; + unsigned int phy_bus_width; + enum rk_if_color_format hdmi_output; + // struct rockchip_drm_sub_dev sub_dev; + + u8 max_frl_rate_per_lane; + u8 max_lanes; + // struct rockchip_drm_dsc_cap dsc_cap; + // struct next_hdr_sink_data next_hdr_data; + struct dw_hdmi_link_config link_cfg; + struct gpio_desc *enable_gpio; + + struct delayed_work work; + struct workqueue_struct *workqueue; }; static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) @@ -202,13 +361,830 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { /*pixelclk symbol term vlev*/ { 74250000, 0x8009, 0x0004, 0x0272}, { 148500000, 0x802b, 0x0004, 0x028d}, + { 165000000, 0x802b, 0x0004, 0x0209}, { 297000000, 0x8039, 0x0005, 0x028d}, + { 594000000, 0x8039, 0x0000, 0x019d}, { ~0UL, 0x0000, 0x0000, 0x0000} }; +enum ROW_INDEX_BPP { + ROW_INDEX_6BPP = 0, + ROW_INDEX_8BPP, + ROW_INDEX_10BPP, + ROW_INDEX_12BPP, + ROW_INDEX_23BPP, + MAX_ROW_INDEX +}; + +enum COLUMN_INDEX_BPC { + COLUMN_INDEX_8BPC = 0, + COLUMN_INDEX_10BPC, + COLUMN_INDEX_12BPC, + COLUMN_INDEX_14BPC, + COLUMN_INDEX_16BPC, + MAX_COLUMN_INDEX +}; + +#define PPS_TABLE_LEN 8 +#define PPS_BPP_LEN 4 +#define PPS_BPC_LEN 2 + +struct pps_data { + u32 pic_width; + u32 pic_height; + u32 slice_width; + u32 slice_height; + bool convert_rgb; + u8 bpc; + u8 bpp; + u8 raw_pps[128]; +}; + +#if 0 +/* + * Selected Rate Control Related Parameter Recommended Values + * from DSC_v1.11 spec & C Model release: DSC_model_20161212 + */ +static struct pps_data pps_datas[PPS_TABLE_LEN] = { + { + /* 7680x4320/960X96 rgb 8bpc 12bpp */ + 7680, 4320, 960, 96, 1, 8, 192, + { + 0x12, 0x00, 0x00, 0x8d, 0x30, 0xc0, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0, + 0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9, + 0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa, + 0x08, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00, + 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x00, 0x82, 0x00, 0xc0, 0x09, 0x00, + 0x09, 0x7e, 0x19, 0xbc, 0x19, 0xba, 0x19, 0xf8, + 0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76, + 0x2a, 0x76, 0x2a, 0x74, 0x3a, 0xb4, 0x52, 0xf4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, + { + /* 7680x4320/960X96 rgb 8bpc 11bpp */ + 7680, 4320, 960, 96, 1, 8, 176, + { + 0x12, 0x00, 0x00, 0x8d, 0x30, 0xb0, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28, + 0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0, + 0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33, + 0x0f, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00, + 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x00, 0x82, 0x01, 0x00, 0x09, 0x40, + 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, + 0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76, + 0x2a, 0x76, 0x2a, 0xb4, 0x3a, 0xb4, 0x52, 0xf4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, + { + /* 7680x4320/960X96 rgb 8bpc 10bpp */ + 7680, 4320, 960, 96, 1, 8, 160, + { + 0x12, 0x00, 0x00, 0x8d, 0x30, 0xa0, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0, + 0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0, + 0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb, + 0x16, 0x00, 0x10, 0xec, 0x03, 0x0c, 0x20, 0x00, + 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40, + 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, + 0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6, + 0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x5b, 0x34, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, + { + /* 7680x4320/960X96 rgb 8bpc 9bpp */ + 7680, 4320, 960, 96, 1, 8, 144, + { + 0x12, 0x00, 0x00, 0x8d, 0x30, 0x90, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38, + 0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7, + 0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa, + 0x17, 0x00, 0x10, 0xf1, 0x03, 0x0c, 0x20, 0x00, + 0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40, + 0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8, + 0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6, + 0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x63, 0x74, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, + { + /* 7680x4320/960X96 rgb 10bpc 12bpp */ + 7680, 4320, 960, 96, 1, 10, 192, + { + 0x12, 0x00, 0x00, 0xad, 0x30, 0xc0, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0, + 0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9, + 0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa, + 0x08, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00, + 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x01, 0x02, 0x11, 0x80, 0x22, 0x00, + 0x22, 0x7e, 0x32, 0xbc, 0x32, 0xba, 0x3a, 0xf8, + 0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76, + 0x4b, 0x76, 0x4b, 0x74, 0x5b, 0xb4, 0x73, 0xf4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, + { + /* 7680x4320/960X96 rgb 10bpc 11bpp */ + 7680, 4320, 960, 96, 1, 10, 176, + { + 0x12, 0x00, 0x00, 0xad, 0x30, 0xb0, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28, + 0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0, + 0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33, + 0x0f, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00, + 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x01, 0x42, 0x19, 0xc0, 0x2a, 0x40, + 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, + 0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76, + 0x4b, 0x76, 0x4b, 0xb4, 0x5b, 0xb4, 0x73, 0xf4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, + { + /* 7680x4320/960X96 rgb 10bpc 10bpp */ + 7680, 4320, 960, 96, 1, 10, 160, + { + 0x12, 0x00, 0x00, 0xad, 0x30, 0xa0, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0, + 0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0, + 0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb, + 0x16, 0x00, 0x10, 0xec, 0x07, 0x10, 0x20, 0x00, + 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40, + 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, + 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6, + 0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x7c, 0x34, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, + { + /* 7680x4320/960X96 rgb 10bpc 9bpp */ + 7680, 4320, 960, 96, 1, 10, 144, + { + 0x12, 0x00, 0x00, 0xad, 0x30, 0x90, 0x10, 0xe0, + 0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38, + 0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7, + 0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa, + 0x17, 0x00, 0x10, 0xf1, 0x07, 0x10, 0x20, 0x00, + 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38, + 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b, + 0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40, + 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, + 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6, + 0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x84, 0x74, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, + }, +}; + +static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_RGB101010_1X30: + case MEDIA_BUS_FMT_RGB121212_1X36: + case MEDIA_BUS_FMT_RGB161616_1X48: + return true; + + default: + return false; + } +} + +static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_YUV10_1X30: + case MEDIA_BUS_FMT_YUV12_1X36: + case MEDIA_BUS_FMT_YUV16_1X48: + return true; + + default: + return false; + } +} +#endif + +static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_UYVY10_1X20: + case MEDIA_BUS_FMT_UYVY12_1X24: + return true; + + default: + return false; + } +} + +static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + case MEDIA_BUS_FMT_UYYVYY12_0_5X36: + case MEDIA_BUS_FMT_UYYVYY16_0_5X48: + return true; + + default: + return false; + } +} + +static int hdmi_bus_fmt_color_depth(unsigned int bus_format) +{ + switch (bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + return 8; + + case MEDIA_BUS_FMT_RGB101010_1X30: + case MEDIA_BUS_FMT_YUV10_1X30: + case MEDIA_BUS_FMT_UYVY10_1X20: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + return 10; + + case MEDIA_BUS_FMT_RGB121212_1X36: + case MEDIA_BUS_FMT_YUV12_1X36: + case MEDIA_BUS_FMT_UYVY12_1X24: + case MEDIA_BUS_FMT_UYYVYY12_0_5X36: + return 12; + + case MEDIA_BUS_FMT_RGB161616_1X48: + case MEDIA_BUS_FMT_YUV16_1X48: + case MEDIA_BUS_FMT_UYYVYY16_0_5X48: + return 16; + + default: + return 0; + } +} + +static unsigned int +hdmi_get_tmdsclock(struct rockchip_hdmi *hdmi, unsigned long pixelclock) +{ + unsigned int tmdsclock = pixelclock; + unsigned int depth = + hdmi_bus_fmt_color_depth(hdmi->output_bus_format); + + if (!hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format)) { + switch (depth) { + case 16: + tmdsclock = pixelclock * 2; + break; + case 12: + tmdsclock = pixelclock * 3 / 2; + break; + case 10: + tmdsclock = pixelclock * 5 / 4; + break; + default: + break; + } + } + + return tmdsclock; +} + +static int rockchip_hdmi_match_by_id(struct device *dev, const void *data) +{ + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + const unsigned int *id = data; + + return hdmi->id == *id; +} + +static struct rockchip_hdmi * +rockchip_hdmi_find_by_id(struct device_driver *drv, unsigned int id) +{ + struct device *dev; + + dev = driver_find_device(drv, NULL, &id, rockchip_hdmi_match_by_id); + if (!dev) + return NULL; + + return dev_get_drvdata(dev); +} + +static void hdmi_select_link_config(struct rockchip_hdmi *hdmi, + struct drm_crtc_state *crtc_state, + unsigned int tmdsclk) +{ + struct drm_display_mode mode; + int max_lanes, max_rate_per_lane; + // int max_dsc_lanes, max_dsc_rate_per_lane; + unsigned long max_frl_rate; + + drm_mode_copy(&mode, &crtc_state->mode); + + max_lanes = hdmi->max_lanes; + max_rate_per_lane = hdmi->max_frl_rate_per_lane; + max_frl_rate = max_lanes * max_rate_per_lane * 1000000; + + hdmi->link_cfg.dsc_mode = false; + hdmi->link_cfg.frl_lanes = max_lanes; + hdmi->link_cfg.rate_per_lane = max_rate_per_lane; + + if (!max_frl_rate || (tmdsclk < HDMI20_MAX_RATE && mode.clock < HDMI20_MAX_RATE)) { + hdmi->link_cfg.frl_mode = false; + return; + } + + hdmi->link_cfg.frl_mode = true; + dev_warn(hdmi->dev, "use unsupported frl hdmi mode\n"); + + // if (!hdmi->dsc_cap.v_1p2) + // return; + // + // max_dsc_lanes = hdmi->dsc_cap.max_lanes; + // max_dsc_rate_per_lane = + // hdmi->dsc_cap.max_frl_rate_per_lane; + // + // if (mode.clock >= HDMI_8K60_RATE && + // !hdmi_bus_fmt_is_yuv420(hdmi->bus_format) && + // !hdmi_bus_fmt_is_yuv422(hdmi->bus_format)) { + // hdmi->link_cfg.dsc_mode = true; + // hdmi->link_cfg.frl_lanes = max_dsc_lanes; + // hdmi->link_cfg.rate_per_lane = max_dsc_rate_per_lane; + // } else { + // hdmi->link_cfg.dsc_mode = false; + // hdmi->link_cfg.frl_lanes = max_lanes; + // hdmi->link_cfg.rate_per_lane = max_rate_per_lane; + // } +} + +///////////////////////////////////////////////////////////////////////////////////// +/* CC: disable DSC */ +#if 0 +static int hdmi_dsc_get_slice_height(int vactive) +{ + int slice_height; + + /* + * Slice Height determination : HDMI2.1 Section 7.7.5.2 + * Select smallest slice height >=96, that results in a valid PPS and + * requires minimum padding lines required for final slice. + * + * Assumption : Vactive is even. + */ + for (slice_height = 96; slice_height <= vactive; slice_height += 2) + if (vactive % slice_height == 0) + return slice_height; + + return 0; +} + +static int hdmi_dsc_get_num_slices(struct rockchip_hdmi *hdmi, + struct drm_crtc_state *crtc_state, + int src_max_slices, int src_max_slice_width, + int hdmi_max_slices, int hdmi_throughput) +{ +/* Pixel rates in KPixels/sec */ +#define HDMI_DSC_PEAK_PIXEL_RATE 2720000 +/* + * Rates at which the source and sink are required to process pixels in each + * slice, can be two levels: either at least 340000KHz or at least 40000KHz. + */ +#define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 +#define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 + +/* Spec limits the slice width to 2720 pixels */ +#define MAX_HDMI_SLICE_WIDTH 2720 + int kslice_adjust; + int adjusted_clk_khz; + int min_slices; + int target_slices; + int max_throughput; /* max clock freq. in khz per slice */ + int max_slice_width; + int slice_width; + int pixel_clock = crtc_state->mode.clock; + + if (!hdmi_throughput) + return 0; + + /* + * Slice Width determination : HDMI2.1 Section 7.7.5.1 + * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as + * for 4:4:4 is 1.0. Multiplying these factors by 10 and later + * dividing adjusted clock value by 10. + */ + if (hdmi_bus_fmt_is_yuv444(hdmi->output_bus_format) || + hdmi_bus_fmt_is_rgb(hdmi->output_bus_format)) + kslice_adjust = 10; + else + kslice_adjust = 5; + + /* + * As per spec, the rate at which the source and the sink process + * the pixels per slice are at two levels: at least 340Mhz or 400Mhz. + * This depends upon the pixel clock rate and output formats + * (kslice adjust). + * If pixel clock * kslice adjust >= 2720MHz slices can be processed + * at max 340MHz, otherwise they can be processed at max 400MHz. + */ + + adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); + + if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) + max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; + else + max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; + + /* + * Taking into account the sink's capability for maximum + * clock per slice (in MHz) as read from HF-VSDB. + */ + max_throughput = min(max_throughput, hdmi_throughput * 1000); + + min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); + max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); + + /* + * Keep on increasing the num of slices/line, starting from min_slices + * per line till we get such a number, for which the slice_width is + * just less than max_slice_width. The slices/line selected should be + * less than or equal to the max horizontal slices that the combination + * of PCON encoder and HDMI decoder can support. + */ + do { + if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) + target_slices = 1; + else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) + target_slices = 2; + else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) + target_slices = 4; + else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) + target_slices = 8; + else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) + target_slices = 12; + else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) + target_slices = 16; + else + return 0; + + slice_width = DIV_ROUND_UP(crtc_state->mode.hdisplay, target_slices); + if (slice_width > max_slice_width) + min_slices = target_slices + 1; + } while (slice_width > max_slice_width); + + return target_slices; +} + +static int hdmi_dsc_slices(struct rockchip_hdmi *hdmi, + struct drm_crtc_state *crtc_state) +{ + int hdmi_throughput = hdmi->dsc_cap.clk_per_slice; + int hdmi_max_slices = hdmi->dsc_cap.max_slices; + int rk_max_slices = 8; + int rk_max_slice_width = 2048; + + return hdmi_dsc_get_num_slices(hdmi, crtc_state, rk_max_slices, + rk_max_slice_width, + hdmi_max_slices, hdmi_throughput); +} + +static int +hdmi_dsc_get_bpp(struct rockchip_hdmi *hdmi, int src_fractional_bpp, + int slice_width, int num_slices, bool hdmi_all_bpp, + int hdmi_max_chunk_bytes) +{ + int max_dsc_bpp, min_dsc_bpp; + int target_bytes; + bool bpp_found = false; + int bpp_decrement_x16; + int bpp_target; + int bpp_target_x16; + + /* + * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec + * Start with the max bpp and keep on decrementing with + * fractional bpp, if supported by PCON DSC encoder + * + * for each bpp we check if no of bytes can be supported by HDMI sink + */ + + /* only 9\10\12 bpp was tested */ + min_dsc_bpp = 9; + max_dsc_bpp = 12; + + /* + * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink + * Section 7.7.34 : Source shall not enable compressed Video + * Transport with bpp_target settings above 12 bpp unless + * DSC_all_bpp is set to 1. + */ + if (!hdmi_all_bpp) + max_dsc_bpp = min(max_dsc_bpp, 12); + + /* + * The Sink has a limit of compressed data in bytes for a scanline, + * as described in max_chunk_bytes field in HFVSDB block of edid. + * The no. of bytes depend on the target bits per pixel that the + * source configures. So we start with the max_bpp and calculate + * the target_chunk_bytes. We keep on decrementing the target_bpp, + * till we get the target_chunk_bytes just less than what the sink's + * max_chunk_bytes, or else till we reach the min_dsc_bpp. + * + * The decrement is according to the fractional support from PCON DSC + * encoder. For fractional BPP we use bpp_target as a multiple of 16. + * + * bpp_target_x16 = bpp_target * 16 + * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps + * {1/16, 1/8, 1/4, 1/2, 1} respectively. + */ + + bpp_target = max_dsc_bpp; + + /* src does not support fractional bpp implies decrement by 16 for bppx16 */ + if (!src_fractional_bpp) + src_fractional_bpp = 1; + bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); + bpp_target_x16 = bpp_target * 16; + + while (bpp_target_x16 > (min_dsc_bpp * 16)) { + int bpp; + + bpp = DIV_ROUND_UP(bpp_target_x16, 16); + target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); + if (target_bytes <= hdmi_max_chunk_bytes) { + bpp_found = true; + break; + } + bpp_target_x16 -= bpp_decrement_x16; + } + if (bpp_found) + return bpp_target_x16; + + return 0; +} + +static int +dw_hdmi_dsc_bpp(struct rockchip_hdmi *hdmi, + int num_slices, int slice_width) +{ + bool hdmi_all_bpp = hdmi->dsc_cap.all_bpp; + int fractional_bpp = 0; + int hdmi_max_chunk_bytes = hdmi->dsc_cap.total_chunk_kbytes * 1024; + + return hdmi_dsc_get_bpp(hdmi, fractional_bpp, slice_width, + num_slices, hdmi_all_bpp, + hdmi_max_chunk_bytes); +} + +static int dw_hdmi_qp_set_link_cfg(struct rockchip_hdmi *hdmi, + u16 pic_width, u16 pic_height, + u16 slice_width, u16 slice_height, + u16 bits_per_pixel, u8 bits_per_component) +{ + int i; + + for (i = 0; i < PPS_TABLE_LEN; i++) + if (pic_width == pps_datas[i].pic_width && + pic_height == pps_datas[i].pic_height && + slice_width == pps_datas[i].slice_width && + slice_height == pps_datas[i].slice_height && + bits_per_component == pps_datas[i].bpc && + bits_per_pixel == pps_datas[i].bpp && + hdmi_bus_fmt_is_rgb(hdmi->output_bus_format) == pps_datas[i].convert_rgb) + break; + + if (i == PPS_TABLE_LEN) { + dev_err(hdmi->dev, "can't find pps cfg!\n"); + return -EINVAL; + } + + memcpy(hdmi->link_cfg.pps_payload, pps_datas[i].raw_pps, 128); + hdmi->link_cfg.hcactive = DIV_ROUND_UP(slice_width * (bits_per_pixel / 16), 8) * + (pic_width / slice_width); + + return 0; +} + +static void dw_hdmi_qp_dsc_configure(struct rockchip_hdmi *hdmi, + struct rockchip_crtc_state *s, + struct drm_crtc_state *crtc_state) +{ + int ret; + int slice_height; + int slice_width; + int bits_per_pixel; + int slice_count; + bool hdmi_is_dsc_1_2; + unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->output_bus_format); + + if (!crtc_state) + return; + + hdmi_is_dsc_1_2 = hdmi->dsc_cap.v_1p2; + + if (!hdmi_is_dsc_1_2) + return; + + slice_height = hdmi_dsc_get_slice_height(crtc_state->mode.vdisplay); + if (!slice_height) + return; + + slice_count = hdmi_dsc_slices(hdmi, crtc_state); + if (!slice_count) + return; + + slice_width = DIV_ROUND_UP(crtc_state->mode.hdisplay, slice_count); + + bits_per_pixel = dw_hdmi_dsc_bpp(hdmi, slice_count, slice_width); + if (!bits_per_pixel) + return; + + ret = dw_hdmi_qp_set_link_cfg(hdmi, crtc_state->mode.hdisplay, + crtc_state->mode.vdisplay, slice_width, + slice_height, bits_per_pixel, depth); + + if (ret) { + dev_err(hdmi->dev, "set vdsc cfg failed\n"); + return; + } + dev_info(hdmi->dev, "dsc_enable\n"); + s->dsc_enable = 1; + s->dsc_sink_cap.version_major = 1; + s->dsc_sink_cap.version_minor = 2; + s->dsc_sink_cap.slice_width = slice_width; + s->dsc_sink_cap.slice_height = slice_height; + s->dsc_sink_cap.target_bits_per_pixel_x16 = bits_per_pixel; + s->dsc_sink_cap.block_pred = 1; + s->dsc_sink_cap.native_420 = 0; + + memcpy(&s->pps, hdmi->link_cfg.pps_payload, 128); +} +#endif +///////////////////////////////////////////////////////////////////////////////////////// + +// static int rockchip_hdmi_update_phy_table(struct rockchip_hdmi *hdmi, +// u32 *config, +// int phy_table_size) +// { +// int i; +// +// if (phy_table_size > ARRAY_SIZE(rockchip_phy_config)) { +// dev_err(hdmi->dev, "phy table array number is out of range\n"); +// return -E2BIG; +// } +// +// for (i = 0; i < phy_table_size; i++) { +// if (config[i * 4] != 0) +// rockchip_phy_config[i].mpixelclock = (u64)config[i * 4]; +// else +// rockchip_phy_config[i].mpixelclock = ~0UL; +// rockchip_phy_config[i].sym_ctr = (u16)config[i * 4 + 1]; +// rockchip_phy_config[i].term = (u16)config[i * 4 + 2]; +// rockchip_phy_config[i].vlev_ctr = (u16)config[i * 4 + 3]; +// } +// +// return 0; +// } + +static void repo_hpd_event(struct work_struct *p_work) +{ + struct rockchip_hdmi *hdmi = container_of(p_work, struct rockchip_hdmi, work.work); + bool change; + + change = drm_helper_hpd_irq_event(hdmi->drm_dev); + if (change) { + dev_dbg(hdmi->dev, "hpd stat changed:%d\n", hdmi->hpd_stat); + // dw_hdmi_qp_cec_set_hpd(hdmi->hdmi_qp, hdmi->hpd_stat, change); + } +} + +static irqreturn_t rockchip_hdmi_hardirq(int irq, void *dev_id) +{ + struct rockchip_hdmi *hdmi = dev_id; + u32 intr_stat, val; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); + + if (intr_stat) { + dev_dbg(hdmi->dev, "hpd irq %#x\n", intr_stat); + + if (!hdmi->id) + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, + RK3588_HDMI0_HPD_INT_MSK); + else + val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, + RK3588_HDMI1_HPD_INT_MSK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static irqreturn_t rockchip_hdmi_irq(int irq, void *dev_id) +{ + struct rockchip_hdmi *hdmi = dev_id; + u32 intr_stat, val; + int msecs; + bool stat; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); + + if (!intr_stat) + return IRQ_NONE; + + if (!hdmi->id) { + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, + RK3588_HDMI0_HPD_INT_CLR); + if (intr_stat & RK3588_HDMI0_LEVEL_INT) + stat = true; + else + stat = false; + } else { + val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, + RK3588_HDMI1_HPD_INT_CLR); + if (intr_stat & RK3588_HDMI1_LEVEL_INT) + stat = true; + else + stat = false; + } + + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + if (stat) { + hdmi->hpd_stat = true; + msecs = 150; + } else { + hdmi->hpd_stat = false; + msecs = 20; + } + mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(msecs)); + + if (!hdmi->id) { + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, + RK3588_HDMI0_HPD_INT_CLR) | + HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); + } else { + val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, + RK3588_HDMI1_HPD_INT_CLR) | + HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK); + } + + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + return IRQ_HANDLED; +} + static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) { struct device_node *np = hdmi->dev->of_node; + int ret; hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); if (IS_ERR(hdmi->regmap)) { @@ -216,6 +1192,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) return PTR_ERR(hdmi->regmap); } + if (hdmi->is_hdmi_qp) { + hdmi->vo1_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,vo1_grf"); + if (IS_ERR(hdmi->vo1_regmap)) { + DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,vo1_grf\n"); + return PTR_ERR(hdmi->vo1_regmap); + } + } + hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); if (!hdmi->ref_clk) hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); @@ -245,6 +1229,79 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) if (IS_ERR(hdmi->avdd_1v8)) return PTR_ERR(hdmi->avdd_1v8); + hdmi->hclk_vio = devm_clk_get(hdmi->dev, "hclk_vio"); + if (PTR_ERR(hdmi->hclk_vio) == -ENOENT) { + hdmi->hclk_vio = NULL; + } else if (PTR_ERR(hdmi->hclk_vio) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(hdmi->hclk_vio)) { + dev_err(hdmi->dev, "failed to get hclk_vio clock\n"); + return PTR_ERR(hdmi->hclk_vio); + } + + hdmi->hclk_vop = devm_clk_get(hdmi->dev, "hclk"); + if (PTR_ERR(hdmi->hclk_vop) == -ENOENT) { + hdmi->hclk_vop = NULL; + } else if (PTR_ERR(hdmi->hclk_vop) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(hdmi->hclk_vop)) { + dev_err(hdmi->dev, "failed to get hclk_vop clock\n"); + return PTR_ERR(hdmi->hclk_vop); + } + + hdmi->aud_clk = devm_clk_get_optional(hdmi->dev, "aud"); + if (IS_ERR(hdmi->aud_clk)) { + dev_err_probe(hdmi->dev, PTR_ERR(hdmi->aud_clk), + "failed to get aud_clk clock\n"); + return PTR_ERR(hdmi->aud_clk); + } + + hdmi->hpd_clk = devm_clk_get_optional(hdmi->dev, "hpd"); + if (IS_ERR(hdmi->hpd_clk)) { + dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hpd_clk), + "failed to get hpd_clk clock\n"); + return PTR_ERR(hdmi->hpd_clk); + } + + hdmi->hclk_vo1 = devm_clk_get_optional(hdmi->dev, "hclk_vo1"); + if (IS_ERR(hdmi->hclk_vo1)) { + dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hclk_vo1), + "failed to get hclk_vo1 clock\n"); + return PTR_ERR(hdmi->hclk_vo1); + } + + hdmi->earc_clk = devm_clk_get_optional(hdmi->dev, "earc"); + if (IS_ERR(hdmi->earc_clk)) { + dev_err_probe(hdmi->dev, PTR_ERR(hdmi->earc_clk), + "failed to get earc_clk clock\n"); + return PTR_ERR(hdmi->earc_clk); + } + + hdmi->hdmitx_ref = devm_clk_get_optional(hdmi->dev, "hdmitx_ref"); + if (IS_ERR(hdmi->hdmitx_ref)) { + dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hdmitx_ref), + "failed to get hdmitx_ref clock\n"); + return PTR_ERR(hdmi->hdmitx_ref); + } + + hdmi->pclk = devm_clk_get_optional(hdmi->dev, "pclk"); + if (IS_ERR(hdmi->pclk)) { + dev_err_probe(hdmi->dev, PTR_ERR(hdmi->pclk), + "failed to get pclk clock\n"); + return PTR_ERR(hdmi->pclk); + } + + hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable", + GPIOD_OUT_HIGH); + if (IS_ERR(hdmi->enable_gpio)) { + ret = PTR_ERR(hdmi->enable_gpio); + dev_err(hdmi->dev, "failed to request enable GPIO: %d\n", ret); + return ret; + } + + hdmi->skip_check_420_mode = + of_property_read_bool(np, "skip-check-420-mode"); + return 0; } @@ -283,9 +1340,114 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, return MODE_BAD; } +/* [CC:] enable downstream mode_valid() */ +// static enum drm_mode_status +// dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, void *data, +// const struct drm_display_info *info, +// const struct drm_display_mode *mode) +// { +// struct drm_encoder *encoder = connector->encoder; +// enum drm_mode_status status = MODE_OK; +// struct drm_device *dev = connector->dev; +// struct rockchip_drm_private *priv = dev->dev_private; +// struct drm_crtc *crtc; +// struct rockchip_hdmi *hdmi; +// +// /* +// * Pixel clocks we support are always < 2GHz and so fit in an +// * int. We should make sure source rate does too so we don't get +// * overflow when we multiply by 1000. +// */ +// if (mode->clock > INT_MAX / 1000) +// return MODE_BAD; +// +// if (!encoder) { +// const struct drm_connector_helper_funcs *funcs; +// +// funcs = connector->helper_private; +// if (funcs->atomic_best_encoder) +// encoder = funcs->atomic_best_encoder(connector, +// connector->state); +// else +// encoder = funcs->best_encoder(connector); +// } +// +// if (!encoder || !encoder->possible_crtcs) +// return MODE_BAD; +// +// hdmi = to_rockchip_hdmi(encoder); +// +// /* +// * If sink max TMDS clock < 340MHz, we should check the mode pixel +// * clock > 340MHz is YCbCr420 or not and whether the platform supports +// * YCbCr420. +// */ +// if (!hdmi->skip_check_420_mode) { +// if (mode->clock > 340000 && +// connector->display_info.max_tmds_clock < 340000 && +// (!drm_mode_is_420(&connector->display_info, mode) || +// !connector->ycbcr_420_allowed)) +// return MODE_BAD; +// +// if (hdmi->max_tmdsclk <= 340000 && mode->clock > 340000 && +// !drm_mode_is_420(&connector->display_info, mode)) +// return MODE_BAD; +// }; +// +// if (hdmi->phy) { +// if (hdmi->is_hdmi_qp) +// phy_set_bus_width(hdmi->phy, mode->clock * 10); +// else +// phy_set_bus_width(hdmi->phy, 8); +// } +// +// /* +// * ensure all drm display mode can work, if someone want support more +// * resolutions, please limit the possible_crtc, only connect to +// * needed crtc. +// */ +// drm_for_each_crtc(crtc, connector->dev) { +// int pipe = drm_crtc_index(crtc); +// const struct rockchip_crtc_funcs *funcs = +// priv->crtc_funcs[pipe]; +// +// if (!(encoder->possible_crtcs & drm_crtc_mask(crtc))) +// continue; +// if (!funcs || !funcs->mode_valid) +// continue; +// +// status = funcs->mode_valid(crtc, mode, +// DRM_MODE_CONNECTOR_HDMIA); +// if (status != MODE_OK) +// return status; +// } +// +// return status; +// } +// static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) { + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + // struct drm_crtc *crtc = encoder->crtc; + // struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); + // + // if (crtc->state->active_changed) { + // if (hdmi->plat_data->split_mode) { + // s->output_if &= ~(VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1); + // } else { + // if (!hdmi->id) + // s->output_if &= ~VOP_OUTPUT_IF_HDMI1; + // else + // s->output_if &= ~VOP_OUTPUT_IF_HDMI0; + // } + // } + /* + * when plug out hdmi it will be switch cvbs and then phy bus width + * must be set as 8 + */ + if (hdmi->phy) + phy_set_bus_width(hdmi->phy, 8); } static bool @@ -301,6 +1463,27 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *adj_mode) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + struct drm_crtc *crtc; + struct rockchip_crtc_state *s; + + if (!encoder->crtc) + return; + crtc = encoder->crtc; + + if (!crtc->state) + return; + s = to_rockchip_crtc_state(crtc->state); + + if (!s) + return; + + if (hdmi->is_hdmi_qp) { + // s->dsc_enable = 0; + // if (hdmi->link_cfg.dsc_mode) + // dw_hdmi_qp_dsc_configure(hdmi, s, crtc->state); + + phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); + } clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); } @@ -308,14 +1491,25 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + struct drm_crtc *crtc = encoder->crtc; u32 val; + int mux; int ret; + if (WARN_ON(!crtc || !crtc->state)) + return; + + if (hdmi->phy) + phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); + + clk_set_rate(hdmi->ref_clk, + crtc->state->adjusted_mode.crtc_clock * 1000); + if (hdmi->chip_data->lcdsel_grf_reg < 0) return; - ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); - if (ret) + mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); + if (mux) val = hdmi->chip_data->lcdsel_lit; else val = hdmi->chip_data->lcdsel_big; @@ -330,24 +1524,992 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) if (ret != 0) DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); + if (hdmi->chip_data->lcdsel_grf_reg == RK3288_GRF_SOC_CON6) { + struct rockchip_crtc_state *s = + to_rockchip_crtc_state(crtc->state); + u32 mode_mask = mux ? RK3288_HDMI_LCDC1_YUV420 : + RK3288_HDMI_LCDC0_YUV420; + + if (s->output_mode == ROCKCHIP_OUT_MODE_YUV420) + val = HIWORD_UPDATE(mode_mask, mode_mask); + else + val = HIWORD_UPDATE(0, mode_mask); + + regmap_write(hdmi->regmap, RK3288_GRF_SOC_CON16, val); + } + clk_disable_unprepare(hdmi->grf_clk); DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", ret ? "LIT" : "BIG"); } -static int -dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static void rk3588_set_link_mode(struct rockchip_hdmi *hdmi) { - struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + int val; + bool is_hdmi0; - s->output_mode = ROCKCHIP_OUT_MODE_AAAA; - s->output_type = DRM_MODE_CONNECTOR_HDMIA; + if (!hdmi->id) + is_hdmi0 = true; + else + is_hdmi0 = false; + + if (!hdmi->link_cfg.frl_mode) { + val = HIWORD_UPDATE(0, RK3588_HDMI21_MASK); + if (is_hdmi0) + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); + else + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); + + val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); + if (is_hdmi0) + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); + else + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); + + return; + } + + val = HIWORD_UPDATE(RK3588_HDMI21_MASK, RK3588_HDMI21_MASK); + if (is_hdmi0) + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); + else + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); + + if (hdmi->link_cfg.dsc_mode) { + val = HIWORD_UPDATE(RK3588_COMPRESS_MODE_MASK | RK3588_COMPRESSED_DATA, + RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); + if (is_hdmi0) + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); + else + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); + } else { + val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); + if (is_hdmi0) + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); + else + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); + } +} + +static void rk3588_set_color_format(struct rockchip_hdmi *hdmi, u64 bus_format, + u32 depth) +{ + u32 val = 0; + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_RGB101010_1X30: + val = HIWORD_UPDATE(0, RK3588_COLOR_FORMAT_MASK); + break; + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + val = HIWORD_UPDATE(RK3588_YUV420, RK3588_COLOR_FORMAT_MASK); + break; + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_YUV10_1X30: + val = HIWORD_UPDATE(RK3588_YUV444, RK3588_COLOR_FORMAT_MASK); + break; + default: + dev_err(hdmi->dev, "can't set correct color format\n"); + return; + } + + if (hdmi->link_cfg.dsc_mode) + val = HIWORD_UPDATE(RK3588_COMPRESSED_DATA, RK3588_COLOR_FORMAT_MASK); + + if (depth == 8) + val |= HIWORD_UPDATE(RK3588_8BPC, RK3588_COLOR_DEPTH_MASK); + else + val |= HIWORD_UPDATE(RK3588_10BPC, RK3588_COLOR_DEPTH_MASK); + + if (!hdmi->id) + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); + else + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); +} + +static void rk3588_set_grf_cfg(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + int color_depth; + + rk3588_set_link_mode(hdmi); + color_depth = hdmi_bus_fmt_color_depth(hdmi->bus_format); + rk3588_set_color_format(hdmi, hdmi->bus_format, color_depth); +} + +static void +dw_hdmi_rockchip_select_output(struct drm_connector_state *conn_state, + struct drm_crtc_state *crtc_state, + struct rockchip_hdmi *hdmi, + unsigned int *color_format, + unsigned int *output_mode, + unsigned long *bus_format, + unsigned int *bus_width, + unsigned long *enc_out_encoding, + unsigned int *eotf) +{ + struct drm_display_info *info = &conn_state->connector->display_info; + struct drm_display_mode mode; + struct hdr_output_metadata *hdr_metadata; + u32 vic; + unsigned long tmdsclock, pixclock; + unsigned int color_depth; + bool support_dc = false; + bool sink_is_hdmi = true; + u32 max_tmds_clock = info->max_tmds_clock; + int output_eotf; + + drm_mode_copy(&mode, &crtc_state->mode); + pixclock = mode.crtc_clock; + // if (hdmi->plat_data->split_mode) { + // drm_mode_convert_to_origin_mode(&mode); + // pixclock /= 2; + // } + + vic = drm_match_cea_mode(&mode); + + if (!hdmi->is_hdmi_qp) + sink_is_hdmi = dw_hdmi_get_output_whether_hdmi(hdmi->hdmi); + + *color_format = RK_IF_FORMAT_RGB; + + switch (hdmi->hdmi_output) { + case RK_IF_FORMAT_YCBCR_HQ: + if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) + *color_format = RK_IF_FORMAT_YCBCR444; + else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) + *color_format = RK_IF_FORMAT_YCBCR422; + else if (conn_state->connector->ycbcr_420_allowed && + drm_mode_is_420(info, &mode) && + (pixclock >= 594000 && !hdmi->is_hdmi_qp)) + *color_format = RK_IF_FORMAT_YCBCR420; + break; + case RK_IF_FORMAT_YCBCR_LQ: + if (conn_state->connector->ycbcr_420_allowed && + drm_mode_is_420(info, &mode) && pixclock >= 594000) + *color_format = RK_IF_FORMAT_YCBCR420; + else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) + *color_format = RK_IF_FORMAT_YCBCR422; + else if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) + *color_format = RK_IF_FORMAT_YCBCR444; + break; + case RK_IF_FORMAT_YCBCR420: + if (conn_state->connector->ycbcr_420_allowed && + drm_mode_is_420(info, &mode) && pixclock >= 594000) + *color_format = RK_IF_FORMAT_YCBCR420; + break; + case RK_IF_FORMAT_YCBCR422: + if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) + *color_format = RK_IF_FORMAT_YCBCR422; + break; + case RK_IF_FORMAT_YCBCR444: + if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) + *color_format = RK_IF_FORMAT_YCBCR444; + break; + case RK_IF_FORMAT_RGB: + default: + break; + } + + if (*color_format == RK_IF_FORMAT_RGB && + info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) + support_dc = true; + if (*color_format == RK_IF_FORMAT_YCBCR444 && + info->edid_hdmi_rgb444_dc_modes & + (DRM_EDID_HDMI_DC_Y444 | DRM_EDID_HDMI_DC_30)) + support_dc = true; + if (*color_format == RK_IF_FORMAT_YCBCR422) + support_dc = true; + if (*color_format == RK_IF_FORMAT_YCBCR420 && + info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) + support_dc = true; + + if (hdmi->colordepth > 8 && support_dc) + color_depth = 10; + else + color_depth = 8; + + if (!sink_is_hdmi) { + *color_format = RK_IF_FORMAT_RGB; + color_depth = 8; + } + + *eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR; + if (conn_state->hdr_output_metadata) { + hdr_metadata = (struct hdr_output_metadata *) + conn_state->hdr_output_metadata->data; + output_eotf = hdr_metadata->hdmi_metadata_type1.eotf; + if (output_eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR && + output_eotf <= HDMI_EOTF_BT_2100_HLG) + *eotf = output_eotf; + } + + hdmi->colorimetry = conn_state->colorspace; + + if ((*eotf > HDMI_EOTF_TRADITIONAL_GAMMA_SDR && + conn_state->connector->hdr_sink_metadata.hdmi_type1.eotf & + BIT(*eotf)) || ((hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_CYCC) && + (hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_YCC))) + *enc_out_encoding = V4L2_YCBCR_ENC_BT2020; + else if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || + (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) + *enc_out_encoding = V4L2_YCBCR_ENC_601; + else + *enc_out_encoding = V4L2_YCBCR_ENC_709; + + if (*enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { + /* BT2020 require color depth at lest 10bit */ + color_depth = 10; + /* We prefer use YCbCr422 to send 10bit */ + if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) + *color_format = RK_IF_FORMAT_YCBCR422; + if (hdmi->is_hdmi_qp) { + if (info->color_formats & DRM_COLOR_FORMAT_YCBCR420) { + if (mode.clock >= 340000) + *color_format = RK_IF_FORMAT_YCBCR420; + else + *color_format = RK_IF_FORMAT_RGB; + } else { + *color_format = RK_IF_FORMAT_RGB; + } + } + } + + if (mode.flags & DRM_MODE_FLAG_DBLCLK) + pixclock *= 2; + if ((mode.flags & DRM_MODE_FLAG_3D_MASK) == + DRM_MODE_FLAG_3D_FRAME_PACKING) + pixclock *= 2; + + if (*color_format == RK_IF_FORMAT_YCBCR422 || color_depth == 8) + tmdsclock = pixclock; + else + tmdsclock = pixclock * (color_depth) / 8; + + if (*color_format == RK_IF_FORMAT_YCBCR420) + tmdsclock /= 2; + + /* XXX: max_tmds_clock of some sink is 0, we think it is 340MHz. */ + if (!max_tmds_clock) + max_tmds_clock = 340000; + + max_tmds_clock = min(max_tmds_clock, hdmi->max_tmdsclk); + + if ((tmdsclock > max_tmds_clock) && !hdmi->is_hdmi_qp) { + if (max_tmds_clock >= 594000) { + color_depth = 8; + } else if (max_tmds_clock > 340000) { + if (drm_mode_is_420(info, &mode) || tmdsclock >= 594000) + *color_format = RK_IF_FORMAT_YCBCR420; + } else { + color_depth = 8; + if (drm_mode_is_420(info, &mode) || tmdsclock >= 594000) + *color_format = RK_IF_FORMAT_YCBCR420; + } + } + + if (hdmi->is_hdmi_qp) { + if (mode.clock >= 340000) { + if (drm_mode_is_420(info, &mode)) + *color_format = RK_IF_FORMAT_YCBCR420; + else + *color_format = RK_IF_FORMAT_RGB; + } else if (tmdsclock > max_tmds_clock) { + color_depth = 8; + if (drm_mode_is_420(info, &mode)) + *color_format = RK_IF_FORMAT_YCBCR420; + } + } + + if (*color_format == RK_IF_FORMAT_YCBCR420) { + *output_mode = ROCKCHIP_OUT_MODE_YUV420; + if (color_depth > 8) + *bus_format = MEDIA_BUS_FMT_UYYVYY10_0_5X30; + else + *bus_format = MEDIA_BUS_FMT_UYYVYY8_0_5X24; + *bus_width = color_depth / 2; + } else { + *output_mode = ROCKCHIP_OUT_MODE_AAAA; + if (color_depth > 8) { + if (*color_format != RK_IF_FORMAT_RGB && + !hdmi->unsupported_yuv_input) + *bus_format = MEDIA_BUS_FMT_YUV10_1X30; + else + *bus_format = MEDIA_BUS_FMT_RGB101010_1X30; + } else { + if (*color_format != RK_IF_FORMAT_RGB && + !hdmi->unsupported_yuv_input) + *bus_format = MEDIA_BUS_FMT_YUV8_1X24; + else + *bus_format = MEDIA_BUS_FMT_RGB888_1X24; + } + if (*color_format == RK_IF_FORMAT_YCBCR422) + *bus_width = 8; + else + *bus_width = color_depth; + } + + hdmi->bus_format = *bus_format; + + if (*color_format == RK_IF_FORMAT_YCBCR422) { + if (color_depth == 12) + hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; + else if (color_depth == 10) + hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; + else + hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; + } else { + hdmi->output_bus_format = *bus_format; + } +} + +static bool +dw_hdmi_rockchip_check_color(struct drm_connector_state *conn_state, + struct rockchip_hdmi *hdmi) +{ + struct drm_crtc_state *crtc_state = conn_state->crtc->state; + unsigned int colorformat; + unsigned long bus_format; + unsigned long output_bus_format = hdmi->output_bus_format; + unsigned long enc_out_encoding = hdmi->enc_out_encoding; + unsigned int eotf, bus_width; + unsigned int output_mode; + + dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, + &colorformat, + &output_mode, &bus_format, &bus_width, + &hdmi->enc_out_encoding, &eotf); + + if (output_bus_format != hdmi->output_bus_format || + enc_out_encoding != hdmi->enc_out_encoding) + return true; + else + return false; +} + +static int +dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + unsigned int colorformat, bus_width, tmdsclk; + struct drm_display_mode mode; + unsigned int output_mode; + unsigned long bus_format; + int color_depth; + bool secondary = false; + + /* + * There are two hdmi but only one encoder in split mode, + * so we need to check twice. + */ +secondary: + drm_mode_copy(&mode, &crtc_state->mode); + + hdmi->vp_id = 0; + // hdmi->vp_id = s->vp_id; + // if (hdmi->plat_data->split_mode) + // drm_mode_convert_to_origin_mode(&mode); + + int eotf; + dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, + &colorformat, + &output_mode, &bus_format, &bus_width, + // &hdmi->enc_out_encoding, &s->eotf); + &hdmi->enc_out_encoding, &eotf); + + s->bus_format = bus_format; + if (hdmi->is_hdmi_qp) { + color_depth = hdmi_bus_fmt_color_depth(bus_format); + tmdsclk = hdmi_get_tmdsclock(hdmi, crtc_state->mode.clock); + if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) + tmdsclk /= 2; + hdmi_select_link_config(hdmi, crtc_state, tmdsclk); + + if (hdmi->link_cfg.frl_mode) { + gpiod_set_value(hdmi->enable_gpio, 0); + /* in the current version, support max 40G frl */ + if (hdmi->link_cfg.rate_per_lane >= 10) { + hdmi->link_cfg.frl_lanes = 4; + hdmi->link_cfg.rate_per_lane = 10; + } + bus_width = hdmi->link_cfg.frl_lanes * + hdmi->link_cfg.rate_per_lane * 1000000; + /* 10 bit color depth and frl mode */ + if (color_depth == 10) + bus_width |= + COLOR_DEPTH_10BIT | HDMI_FRL_MODE; + else + bus_width |= HDMI_FRL_MODE; + } else { + gpiod_set_value(hdmi->enable_gpio, 1); + bus_width = hdmi_get_tmdsclock(hdmi, mode.clock * 10); + if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) + bus_width /= 2; + + if (color_depth == 10) + bus_width |= COLOR_DEPTH_10BIT; + } + } + + hdmi->phy_bus_width = bus_width; + + if (hdmi->phy) + phy_set_bus_width(hdmi->phy, bus_width); + + s->output_type = DRM_MODE_CONNECTOR_HDMIA; + // s->tv_state = &conn_state->tv; + // + // if (hdmi->plat_data->split_mode) { + // s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; + // if (hdmi->plat_data->right && hdmi->id) + // s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; + // s->output_if |= VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1; + // } else { + // if (!hdmi->id) + // s->output_if |= VOP_OUTPUT_IF_HDMI0; + // else + // s->output_if |= VOP_OUTPUT_IF_HDMI1; + // } + + s->output_mode = output_mode; + hdmi->bus_format = s->bus_format; + + if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_BT2020) + s->color_space = V4L2_COLORSPACE_BT2020; + else if (colorformat == RK_IF_FORMAT_RGB) + s->color_space = V4L2_COLORSPACE_DEFAULT; + else if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_709) + s->color_space = V4L2_COLORSPACE_REC709; + else + s->color_space = V4L2_COLORSPACE_SMPTE170M; + + if (hdmi->plat_data->split_mode && !secondary) { + hdmi = rockchip_hdmi_find_by_id(hdmi->dev->driver, !hdmi->id); + secondary = true; + goto secondary; + } return 0; } +static unsigned long +dw_hdmi_rockchip_get_input_bus_format(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return hdmi->bus_format; +} + +static unsigned long +dw_hdmi_rockchip_get_output_bus_format(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return hdmi->output_bus_format; +} + +static unsigned long +dw_hdmi_rockchip_get_enc_in_encoding(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return hdmi->enc_out_encoding; +} + +static unsigned long +dw_hdmi_rockchip_get_enc_out_encoding(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return hdmi->enc_out_encoding; +} + +static unsigned long +dw_hdmi_rockchip_get_quant_range(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return hdmi->hdmi_quant_range; +} + +static struct drm_property * +dw_hdmi_rockchip_get_hdr_property(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return hdmi->hdr_panel_metadata_property; +} + +static struct drm_property_blob * +dw_hdmi_rockchip_get_hdr_blob(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return hdmi->hdr_panel_blob_ptr; +} + +static bool +dw_hdmi_rockchip_get_color_changed(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + bool ret = false; + + if (hdmi->color_changed) + ret = true; + hdmi->color_changed = 0; + + return ret; +} + +#if 0 +static int +dw_hdmi_rockchip_get_edid_dsc_info(void *data, struct edid *edid) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + if (!edid) + return -EINVAL; + + return rockchip_drm_parse_cea_ext(&hdmi->dsc_cap, + &hdmi->max_frl_rate_per_lane, + &hdmi->max_lanes, edid); +} + +static int +dw_hdmi_rockchip_get_next_hdr_data(void *data, struct edid *edid, + struct drm_connector *connector) +{ + int ret; + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + struct next_hdr_sink_data *sink_data = &hdmi->next_hdr_data; + size_t size = sizeof(*sink_data); + struct drm_property *property = hdmi->next_hdr_sink_data_property; + struct drm_property_blob *blob = hdmi->hdr_panel_blob_ptr; + + if (!edid) + return -EINVAL; + + rockchip_drm_parse_next_hdr(sink_data, edid); + + ret = drm_property_replace_global_blob(connector->dev, &blob, size, sink_data, + &connector->base, property); + + return ret; +}; +#endif + +static +struct dw_hdmi_link_config *dw_hdmi_rockchip_get_link_cfg(void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return &hdmi->link_cfg; +} + +#if 0 +static const struct drm_prop_enum_list color_depth_enum_list[] = { + { 0, "Automatic" }, /* Prefer highest color depth */ + { 8, "24bit" }, + { 10, "30bit" }, +}; + +static const struct drm_prop_enum_list drm_hdmi_output_enum_list[] = { + { RK_IF_FORMAT_RGB, "rgb" }, + { RK_IF_FORMAT_YCBCR444, "ycbcr444" }, + { RK_IF_FORMAT_YCBCR422, "ycbcr422" }, + { RK_IF_FORMAT_YCBCR420, "ycbcr420" }, + { RK_IF_FORMAT_YCBCR_HQ, "ycbcr_high_subsampling" }, + { RK_IF_FORMAT_YCBCR_LQ, "ycbcr_low_subsampling" }, + { RK_IF_FORMAT_MAX, "invalid_output" }, +}; + +static const struct drm_prop_enum_list quant_range_enum_list[] = { + { HDMI_QUANTIZATION_RANGE_DEFAULT, "default" }, + { HDMI_QUANTIZATION_RANGE_LIMITED, "limit" }, + { HDMI_QUANTIZATION_RANGE_FULL, "full" }, +}; + +static const struct drm_prop_enum_list output_hdmi_dvi_enum_list[] = { + { 0, "auto" }, + { 1, "force_hdmi" }, + { 2, "force_dvi" }, +}; + +static const struct drm_prop_enum_list output_type_cap_list[] = { + { 0, "DVI" }, + { 1, "HDMI" }, +}; +#endif + +static void +dw_hdmi_rockchip_attach_properties(struct drm_connector *connector, + unsigned int color, int version, + void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + struct drm_property *prop; + // struct rockchip_drm_private *private = connector->dev->dev_private; + + switch (color) { + case MEDIA_BUS_FMT_RGB101010_1X30: + hdmi->hdmi_output = RK_IF_FORMAT_RGB; + hdmi->colordepth = 10; + break; + case MEDIA_BUS_FMT_YUV8_1X24: + hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; + hdmi->colordepth = 8; + break; + case MEDIA_BUS_FMT_YUV10_1X30: + hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; + hdmi->colordepth = 10; + break; + case MEDIA_BUS_FMT_UYVY10_1X20: + hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; + hdmi->colordepth = 10; + break; + case MEDIA_BUS_FMT_UYVY8_1X16: + hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; + hdmi->colordepth = 8; + break; + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; + hdmi->colordepth = 8; + break; + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; + hdmi->colordepth = 10; + break; + default: + hdmi->hdmi_output = RK_IF_FORMAT_RGB; + hdmi->colordepth = 8; + } + + hdmi->bus_format = color; + + if (hdmi->hdmi_output == RK_IF_FORMAT_YCBCR422) { + if (hdmi->colordepth == 12) + hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; + else if (hdmi->colordepth == 10) + hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; + else + hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; + } else { + hdmi->output_bus_format = hdmi->bus_format; + } + +#if 0 + /* RK3368 does not support deep color mode */ + if (!hdmi->color_depth_property && !hdmi->unsupported_deep_color) { + prop = drm_property_create_enum(connector->dev, 0, + RK_IF_PROP_COLOR_DEPTH, + color_depth_enum_list, + ARRAY_SIZE(color_depth_enum_list)); + if (prop) { + hdmi->color_depth_property = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + } + + prop = drm_property_create_enum(connector->dev, 0, RK_IF_PROP_COLOR_FORMAT, + drm_hdmi_output_enum_list, + ARRAY_SIZE(drm_hdmi_output_enum_list)); + if (prop) { + hdmi->hdmi_output_property = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + + prop = drm_property_create_range(connector->dev, 0, + RK_IF_PROP_COLOR_DEPTH_CAPS, + 0, 0xff); + if (prop) { + hdmi->colordepth_capacity = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + + prop = drm_property_create_range(connector->dev, 0, + RK_IF_PROP_COLOR_FORMAT_CAPS, + 0, 0xf); + if (prop) { + hdmi->outputmode_capacity = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + + prop = drm_property_create(connector->dev, + DRM_MODE_PROP_BLOB | + DRM_MODE_PROP_IMMUTABLE, + "HDR_PANEL_METADATA", 0); + if (prop) { + hdmi->hdr_panel_metadata_property = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + + prop = drm_property_create(connector->dev, + DRM_MODE_PROP_BLOB | + DRM_MODE_PROP_IMMUTABLE, + "NEXT_HDR_SINK_DATA", 0); + if (prop) { + hdmi->next_hdr_sink_data_property = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + + prop = drm_property_create_bool(connector->dev, DRM_MODE_PROP_IMMUTABLE, + "USER_SPLIT_MODE"); + if (prop) { + hdmi->user_split_mode_prop = prop; + drm_object_attach_property(&connector->base, prop, + hdmi->user_split_mode ? 1 : 0); + } + + if (!hdmi->is_hdmi_qp) { + prop = drm_property_create_enum(connector->dev, 0, + "output_hdmi_dvi", + output_hdmi_dvi_enum_list, + ARRAY_SIZE(output_hdmi_dvi_enum_list)); + if (prop) { + hdmi->output_hdmi_dvi = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + + prop = drm_property_create_enum(connector->dev, 0, + "output_type_capacity", + output_type_cap_list, + ARRAY_SIZE(output_type_cap_list)); + if (prop) { + hdmi->output_type_capacity = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + + prop = drm_property_create_enum(connector->dev, 0, + "hdmi_quant_range", + quant_range_enum_list, + ARRAY_SIZE(quant_range_enum_list)); + if (prop) { + hdmi->quant_range = prop; + drm_object_attach_property(&connector->base, prop, 0); + } + } +#endif + + prop = connector->dev->mode_config.hdr_output_metadata_property; + if (version >= 0x211a || hdmi->is_hdmi_qp) + drm_object_attach_property(&connector->base, prop, 0); + + if (!drm_mode_create_hdmi_colorspace_property(connector, 0)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, 0); + +#if 0 + // [CC:] if this is not needed, also drop connector_id_prop + if (!private->connector_id_prop) + private->connector_id_prop = drm_property_create_range(connector->dev, + DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_IMMUTABLE, + "CONNECTOR_ID", 0, 0xf); + if (private->connector_id_prop) + drm_object_attach_property(&connector->base, private->connector_id_prop, hdmi->id); +#endif +} + +static void +dw_hdmi_rockchip_destroy_properties(struct drm_connector *connector, + void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + if (hdmi->color_depth_property) { + drm_property_destroy(connector->dev, + hdmi->color_depth_property); + hdmi->color_depth_property = NULL; + } + + if (hdmi->hdmi_output_property) { + drm_property_destroy(connector->dev, + hdmi->hdmi_output_property); + hdmi->hdmi_output_property = NULL; + } + + if (hdmi->colordepth_capacity) { + drm_property_destroy(connector->dev, + hdmi->colordepth_capacity); + hdmi->colordepth_capacity = NULL; + } + + if (hdmi->outputmode_capacity) { + drm_property_destroy(connector->dev, + hdmi->outputmode_capacity); + hdmi->outputmode_capacity = NULL; + } + + if (hdmi->quant_range) { + drm_property_destroy(connector->dev, + hdmi->quant_range); + hdmi->quant_range = NULL; + } + + if (hdmi->hdr_panel_metadata_property) { + drm_property_destroy(connector->dev, + hdmi->hdr_panel_metadata_property); + hdmi->hdr_panel_metadata_property = NULL; + } + + if (hdmi->next_hdr_sink_data_property) { + drm_property_destroy(connector->dev, + hdmi->next_hdr_sink_data_property); + hdmi->next_hdr_sink_data_property = NULL; + } + + if (hdmi->output_hdmi_dvi) { + drm_property_destroy(connector->dev, + hdmi->output_hdmi_dvi); + hdmi->output_hdmi_dvi = NULL; + } + + if (hdmi->output_type_capacity) { + drm_property_destroy(connector->dev, + hdmi->output_type_capacity); + hdmi->output_type_capacity = NULL; + } + + if (hdmi->user_split_mode_prop) { + drm_property_destroy(connector->dev, + hdmi->user_split_mode_prop); + hdmi->user_split_mode_prop = NULL; + } +} + +static int +dw_hdmi_rockchip_set_property(struct drm_connector *connector, + struct drm_connector_state *state, + struct drm_property *property, + u64 val, + void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + struct drm_mode_config *config = &connector->dev->mode_config; + + if (property == hdmi->color_depth_property) { + hdmi->colordepth = val; + /* If hdmi is disconnected, state->crtc is null */ + if (!state->crtc) + return 0; + if (dw_hdmi_rockchip_check_color(state, hdmi)) + hdmi->color_changed++; + return 0; + } else if (property == hdmi->hdmi_output_property) { + hdmi->hdmi_output = val; + if (!state->crtc) + return 0; + if (dw_hdmi_rockchip_check_color(state, hdmi)) + hdmi->color_changed++; + return 0; + } else if (property == hdmi->quant_range) { + u64 quant_range = hdmi->hdmi_quant_range; + + hdmi->hdmi_quant_range = val; + if (quant_range != hdmi->hdmi_quant_range) + dw_hdmi_set_quant_range(hdmi->hdmi); + return 0; + } else if (property == config->hdr_output_metadata_property) { + return 0; + } else if (property == hdmi->output_hdmi_dvi) { + if (hdmi->force_output != val) + hdmi->color_changed++; + hdmi->force_output = val; + dw_hdmi_set_output_type(hdmi->hdmi, val); + return 0; + } else if (property == hdmi->colordepth_capacity) { + return 0; + } else if (property == hdmi->outputmode_capacity) { + return 0; + } else if (property == hdmi->output_type_capacity) { + return 0; + } + + DRM_ERROR("Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); + + return -EINVAL; +} + +static int +dw_hdmi_rockchip_get_property(struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + u64 *val, + void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + struct drm_display_info *info = &connector->display_info; + struct drm_mode_config *config = &connector->dev->mode_config; + + if (property == hdmi->color_depth_property) { + *val = hdmi->colordepth; + return 0; + } else if (property == hdmi->hdmi_output_property) { + *val = hdmi->hdmi_output; + return 0; + } else if (property == hdmi->colordepth_capacity) { + *val = BIT(RK_IF_DEPTH_8); + /* RK3368 only support 8bit */ + if (hdmi->unsupported_deep_color) + return 0; + if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) + *val |= BIT(RK_IF_DEPTH_10); + if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36) + *val |= BIT(RK_IF_DEPTH_12); + if (info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_48) + *val |= BIT(RK_IF_DEPTH_16); + if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) + *val |= BIT(RK_IF_DEPTH_420_10); + if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) + *val |= BIT(RK_IF_DEPTH_420_12); + if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) + *val |= BIT(RK_IF_DEPTH_420_16); + return 0; + } else if (property == hdmi->outputmode_capacity) { + *val = BIT(RK_IF_FORMAT_RGB); + if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) + *val |= BIT(RK_IF_FORMAT_YCBCR444); + if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) + *val |= BIT(RK_IF_FORMAT_YCBCR422); + if (connector->ycbcr_420_allowed && + info->color_formats & DRM_COLOR_FORMAT_YCBCR420) + *val |= BIT(RK_IF_FORMAT_YCBCR420); + return 0; + } else if (property == hdmi->quant_range) { + *val = hdmi->hdmi_quant_range; + return 0; + } else if (property == config->hdr_output_metadata_property) { + *val = state->hdr_output_metadata ? + state->hdr_output_metadata->base.id : 0; + return 0; + } else if (property == hdmi->output_hdmi_dvi) { + *val = hdmi->force_output; + return 0; + } else if (property == hdmi->output_type_capacity) { + *val = dw_hdmi_get_output_type_cap(hdmi->hdmi); + return 0; + } else if (property == hdmi->user_split_mode_prop) { + *val = hdmi->user_split_mode; + return 0; + } + + DRM_ERROR("Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); + + return -EINVAL; +} + +static const struct dw_hdmi_property_ops dw_hdmi_rockchip_property_ops = { + .attach_properties = dw_hdmi_rockchip_attach_properties, + .destroy_properties = dw_hdmi_rockchip_destroy_properties, + .set_property = dw_hdmi_rockchip_set_property, + .get_property = dw_hdmi_rockchip_get_property, +}; + static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, .mode_set = dw_hdmi_rockchip_encoder_mode_set, @@ -356,20 +2518,24 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, }; -static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, - const struct drm_display_info *display, - const struct drm_display_mode *mode) +static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) { struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; - return phy_power_on(hdmi->phy); + while (hdmi->phy->power_count > 0) + phy_power_off(hdmi->phy); } -static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) +static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, + const struct drm_display_info *display, + const struct drm_display_mode *mode) { struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; - phy_power_off(hdmi->phy); + dw_hdmi_rockchip_genphy_disable(dw_hdmi, data); + dw_hdmi_set_high_tmds_clock_ratio(dw_hdmi, display); + + return phy_power_on(hdmi->phy); } static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) @@ -436,6 +2602,90 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) RK3328_HDMI_HPD_IOE)); } +static void dw_hdmi_qp_rockchip_phy_disable(struct dw_hdmi_qp *dw_hdmi, + void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + while (hdmi->phy->power_count > 0) + phy_power_off(hdmi->phy); +} + +static int dw_hdmi_qp_rockchip_genphy_init(struct dw_hdmi_qp *dw_hdmi, void *data, + struct drm_display_mode *mode) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + dw_hdmi_qp_rockchip_phy_disable(dw_hdmi, data); + + return phy_power_on(hdmi->phy); +} + +static enum drm_connector_status +dw_hdmi_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + u32 val; + int ret; + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val); + + if (!hdmi->id) { + if (val & RK3588_HDMI0_LEVEL_INT) { + hdmi->hpd_stat = true; + ret = connector_status_connected; + } else { + hdmi->hpd_stat = false; + ret = connector_status_disconnected; + } + } else { + if (val & RK3588_HDMI1_LEVEL_INT) { + hdmi->hpd_stat = true; + ret = connector_status_connected; + } else { + hdmi->hpd_stat = false; + ret = connector_status_disconnected; + } + } + + return ret; +} + +static void dw_hdmi_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + u32 val; + + if (!hdmi->id) { + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, + RK3588_HDMI0_HPD_INT_CLR) | + HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); + } else { + val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR, + RK3588_HDMI1_HPD_INT_CLR) | + HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK); + } + + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); +} + +static void dw_hdmi_rk3588_phy_set_mode(struct dw_hdmi_qp *dw_hdmi, void *data, + u32 mode_mask, bool enable) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + if (!hdmi->phy) + return; + + /* set phy earc/frl mode */ + if (enable) + hdmi->phy_bus_width |= mode_mask; + else + hdmi->phy_bus_width &= ~mode_mask; + + phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); +} + static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { .init = dw_hdmi_rockchip_genphy_init, .disable = dw_hdmi_rockchip_genphy_disable, @@ -525,6 +2775,30 @@ static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { .use_drm_infoframe = true, }; +static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { + .init = dw_hdmi_qp_rockchip_genphy_init, + .disable = dw_hdmi_qp_rockchip_phy_disable, + .read_hpd = dw_hdmi_rk3588_read_hpd, + .setup_hpd = dw_hdmi_rk3588_setup_hpd, + .set_mode = dw_hdmi_rk3588_phy_set_mode, +}; + +struct rockchip_hdmi_chip_data rk3588_hdmi_chip_data = { + .lcdsel_grf_reg = -1, + .ddc_en_reg = RK3588_GRF_VO1_CON3, + .split_mode = true, +}; + +static const struct dw_hdmi_plat_data rk3588_hdmi_drv_data = { + .phy_data = &rk3588_hdmi_chip_data, + .qp_phy_ops = &rk3588_hdmi_phy_ops, + .phy_name = "samsung_hdptx_phy", + .phy_force_vendor = true, + .ycbcr_420_allowed = true, + .is_hdmi_qp = true, + .use_drm_infoframe = true, +}; + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3228-dw-hdmi", .data = &rk3228_hdmi_drv_data @@ -541,6 +2815,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3568-dw-hdmi", .data = &rk3568_hdmi_drv_data }, + { .compatible = "rockchip,rk3588-dw-hdmi", + .data = &rk3588_hdmi_drv_data + }, {}, }; MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); @@ -550,44 +2827,103 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, { struct platform_device *pdev = to_platform_device(dev); struct dw_hdmi_plat_data *plat_data; - const struct of_device_id *match; struct drm_device *drm = data; struct drm_encoder *encoder; struct rockchip_hdmi *hdmi; + struct rockchip_hdmi *secondary; int ret; + u32 val; if (!pdev->dev.of_node) return -ENODEV; - hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); + hdmi = platform_get_drvdata(pdev); if (!hdmi) return -ENOMEM; - match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); - plat_data = devm_kmemdup(&pdev->dev, match->data, - sizeof(*plat_data), GFP_KERNEL); - if (!plat_data) - return -ENOMEM; + plat_data = hdmi->plat_data; + hdmi->drm_dev = drm; - hdmi->dev = &pdev->dev; - hdmi->plat_data = plat_data; - hdmi->chip_data = plat_data->phy_data; plat_data->phy_data = hdmi; - plat_data->priv_data = hdmi; - encoder = &hdmi->encoder.encoder; + plat_data->get_input_bus_format = + dw_hdmi_rockchip_get_input_bus_format; + plat_data->get_output_bus_format = + dw_hdmi_rockchip_get_output_bus_format; + plat_data->get_enc_in_encoding = + dw_hdmi_rockchip_get_enc_in_encoding; + plat_data->get_enc_out_encoding = + dw_hdmi_rockchip_get_enc_out_encoding; + plat_data->get_quant_range = + dw_hdmi_rockchip_get_quant_range; + plat_data->get_hdr_property = + dw_hdmi_rockchip_get_hdr_property; + plat_data->get_hdr_blob = + dw_hdmi_rockchip_get_hdr_blob; + plat_data->get_color_changed = + dw_hdmi_rockchip_get_color_changed; + // plat_data->get_edid_dsc_info = + // dw_hdmi_rockchip_get_edid_dsc_info; + // plat_data->get_next_hdr_data = + // dw_hdmi_rockchip_get_next_hdr_data; + plat_data->get_link_cfg = dw_hdmi_rockchip_get_link_cfg; + plat_data->set_grf_cfg = rk3588_set_grf_cfg; + // plat_data->convert_to_split_mode = drm_mode_convert_to_split_mode; + // plat_data->convert_to_origin_mode = drm_mode_convert_to_origin_mode; + + plat_data->property_ops = &dw_hdmi_rockchip_property_ops; + + secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id); + /* If don't enable hdmi0 and hdmi1, we don't enable split mode */ + if (hdmi->chip_data->split_mode && secondary) { - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); - rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, - dev->of_node, 0, 0); + /* + * hdmi can only attach bridge and init encoder/connector in the + * last bind hdmi in split mode, or hdmi->hdmi_qp will not be initialized + * and plat_data->left/right will be null pointer. we must check if split + * mode is on and determine the sequence of hdmi bind. + */ + if (device_property_read_bool(dev, "split-mode") || + device_property_read_bool(secondary->dev, "split-mode")) { + plat_data->split_mode = true; + secondary->plat_data->split_mode = true; + if (!secondary->plat_data->first_screen) + plat_data->first_screen = true; + } + + if (device_property_read_bool(dev, "user-split-mode") || + device_property_read_bool(secondary->dev, "user-split-mode")) { + hdmi->user_split_mode = true; + secondary->user_split_mode = true; + } + } + + if (!plat_data->first_screen) { + encoder = &hdmi->encoder.encoder; + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, + dev->of_node, 0, 0); + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (encoder->possible_crtcs == 0) + return -EPROBE_DEFER; + + drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); + // [CC:] consider using drmm_simple_encoder_alloc() + drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); + } + + if (!plat_data->max_tmdsclk) + hdmi->max_tmdsclk = 594000; + else + hdmi->max_tmdsclk = plat_data->max_tmdsclk; - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has - * not been registered yet. Defer probing, and hope that - * the required CRTC is added later. - */ - if (encoder->possible_crtcs == 0) - return -EPROBE_DEFER; + + hdmi->unsupported_yuv_input = plat_data->unsupported_yuv_input; + hdmi->unsupported_deep_color = plat_data->unsupported_deep_color; ret = rockchip_hdmi_parse_dt(hdmi); if (ret) { @@ -596,34 +2932,44 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return ret; } - hdmi->phy = devm_phy_optional_get(dev, "hdmi"); - if (IS_ERR(hdmi->phy)) { - ret = PTR_ERR(hdmi->phy); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); + ret = clk_prepare_enable(hdmi->aud_clk); + if (ret) { + dev_err(hdmi->dev, "Failed to enable HDMI aud_clk: %d\n", ret); return ret; } - ret = regulator_enable(hdmi->avdd_0v9); + ret = clk_prepare_enable(hdmi->hpd_clk); if (ret) { - DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); - goto err_avdd_0v9; + dev_err(hdmi->dev, "Failed to enable HDMI hpd_clk: %d\n", ret); + return ret; } - ret = regulator_enable(hdmi->avdd_1v8); + ret = clk_prepare_enable(hdmi->hclk_vo1); if (ret) { - DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); - goto err_avdd_1v8; + dev_err(hdmi->dev, "Failed to enable HDMI hclk_vo1: %d\n", ret); + return ret; } - ret = clk_prepare_enable(hdmi->ref_clk); + ret = clk_prepare_enable(hdmi->earc_clk); if (ret) { - DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); - goto err_clk; + dev_err(hdmi->dev, "Failed to enable HDMI earc_clk: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(hdmi->hdmitx_ref); + if (ret) { + dev_err(hdmi->dev, "Failed to enable HDMI hdmitx_ref: %d\n", + ret); + return ret; + } + + ret = clk_prepare_enable(hdmi->pclk); + if (ret) { + dev_err(hdmi->dev, "Failed to enable HDMI pclk: %d\n", ret); + return ret; } - if (hdmi->chip_data == &rk3568_chip_data) { + if (hdmi->chip_data->ddc_en_reg == RK3568_GRF_VO_CON1) { regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | RK3568_HDMI_SCLIN_MSK, @@ -631,12 +2977,131 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, RK3568_HDMI_SCLIN_MSK)); } - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); + if (hdmi->is_hdmi_qp) { + if (!hdmi->id) { + val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); + + val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, + RK3588_HDMI0_GRANT_SEL); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); + } else { + val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); + + val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, + RK3588_HDMI1_GRANT_SEL); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); + } + } - platform_set_drvdata(pdev, hdmi); + ret = clk_prepare_enable(hdmi->hclk_vio); + if (ret) { + dev_err(hdmi->dev, "Failed to enable HDMI hclk_vio: %d\n", + ret); + return ret; + } + + ret = clk_prepare_enable(hdmi->hclk_vop); + if (ret) { + dev_err(hdmi->dev, "Failed to enable HDMI hclk_vop: %d\n", + ret); + return ret; + } + + ret = clk_prepare_enable(hdmi->ref_clk); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", + ret); + goto err_clk; + } + + ret = regulator_enable(hdmi->avdd_0v9); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); + goto err_avdd_0v9; + } + + ret = regulator_enable(hdmi->avdd_1v8); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); + goto err_avdd_1v8; + } + + if (!hdmi->id) + val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK); + else + val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, RK3588_HDMI1_HPD_INT_MSK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); + + if (hdmi->is_hdmi_qp) { + hdmi->hpd_irq = platform_get_irq(pdev, 4); + if (hdmi->hpd_irq < 0) + return hdmi->hpd_irq; + + ret = devm_request_threaded_irq(hdmi->dev, hdmi->hpd_irq, + rockchip_hdmi_hardirq, + rockchip_hdmi_irq, + IRQF_SHARED, "dw-hdmi-qp-hpd", + hdmi); + if (ret) + return ret; + } + + hdmi->phy = devm_phy_optional_get(dev, "hdmi"); + if (IS_ERR(hdmi->phy)) { + hdmi->phy = devm_phy_optional_get(dev, "hdmi_phy"); + if (IS_ERR(hdmi->phy)) { + ret = PTR_ERR(hdmi->phy); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); + return ret; + } + } + + if (hdmi->is_hdmi_qp) { + // [CC:] do proper error handling, e.g. clk_disable_unprepare + hdmi->hdmi_qp = dw_hdmi_qp_bind(pdev, &hdmi->encoder.encoder, plat_data); + + if (IS_ERR(hdmi->hdmi_qp)) { + ret = PTR_ERR(hdmi->hdmi_qp); + drm_encoder_cleanup(&hdmi->encoder.encoder); + } + + // if (plat_data->connector) { + // hdmi->sub_dev.connector = plat_data->connector; + // hdmi->sub_dev.of_node = dev->of_node; + // rockchip_drm_register_sub_dev(&hdmi->sub_dev); + // } + + if (plat_data->split_mode && secondary) { + if (device_property_read_bool(dev, "split-mode")) { + plat_data->right = secondary->hdmi_qp; + secondary->plat_data->left = hdmi->hdmi_qp; + } else { + plat_data->left = secondary->hdmi_qp; + secondary->plat_data->right = hdmi->hdmi_qp; + } + } + + return ret; + } - hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); + hdmi->hdmi = dw_hdmi_bind(pdev, &hdmi->encoder.encoder, plat_data); /* * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), @@ -647,11 +3112,24 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, goto err_bind; } + // if (plat_data->connector) { + // hdmi->sub_dev.connector = plat_data->connector; + // hdmi->sub_dev.of_node = dev->of_node; + // rockchip_drm_register_sub_dev(&hdmi->sub_dev); + // } + return 0; err_bind: - drm_encoder_cleanup(encoder); + drm_encoder_cleanup(&hdmi->encoder.encoder); + clk_disable_unprepare(hdmi->aud_clk); clk_disable_unprepare(hdmi->ref_clk); + clk_disable_unprepare(hdmi->hclk_vop); + clk_disable_unprepare(hdmi->hpd_clk); + clk_disable_unprepare(hdmi->hclk_vo1); + clk_disable_unprepare(hdmi->earc_clk); + clk_disable_unprepare(hdmi->hdmitx_ref); + clk_disable_unprepare(hdmi->pclk); err_clk: regulator_disable(hdmi->avdd_1v8); err_avdd_1v8: @@ -665,9 +3143,29 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - dw_hdmi_unbind(hdmi->hdmi); + if (hdmi->is_hdmi_qp) { + cancel_delayed_work(&hdmi->work); + flush_workqueue(hdmi->workqueue); + } + + // if (hdmi->sub_dev.connector) + // rockchip_drm_unregister_sub_dev(&hdmi->sub_dev); + // + if (hdmi->is_hdmi_qp) + dw_hdmi_qp_unbind(hdmi->hdmi_qp); + else + dw_hdmi_unbind(hdmi->hdmi); + drm_encoder_cleanup(&hdmi->encoder.encoder); + + clk_disable_unprepare(hdmi->aud_clk); clk_disable_unprepare(hdmi->ref_clk); + clk_disable_unprepare(hdmi->hclk_vop); + clk_disable_unprepare(hdmi->hpd_clk); + clk_disable_unprepare(hdmi->hclk_vo1); + clk_disable_unprepare(hdmi->earc_clk); + clk_disable_unprepare(hdmi->hdmitx_ref); + clk_disable_unprepare(hdmi->pclk); regulator_disable(hdmi->avdd_1v8); regulator_disable(hdmi->avdd_0v9); @@ -680,30 +3178,142 @@ static const struct component_ops dw_hdmi_rockchip_ops = { static int dw_hdmi_rockchip_probe(struct platform_device *pdev) { + struct rockchip_hdmi *hdmi; + const struct of_device_id *match; + struct dw_hdmi_plat_data *plat_data; + int id; + + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + id = of_alias_get_id(pdev->dev.of_node, "hdmi"); + if (id < 0) + id = 0; + + hdmi->id = id; + hdmi->dev = &pdev->dev; + + match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); + plat_data = devm_kmemdup(&pdev->dev, match->data, + sizeof(*plat_data), GFP_KERNEL); + if (!plat_data) + return -ENOMEM; + + plat_data->id = hdmi->id; + hdmi->plat_data = plat_data; + hdmi->chip_data = plat_data->phy_data; + hdmi->is_hdmi_qp = plat_data->is_hdmi_qp; + + if (hdmi->is_hdmi_qp) { + hdmi->workqueue = create_workqueue("hpd_queue"); + INIT_DELAYED_WORK(&hdmi->work, repo_hpd_event); + } + + platform_set_drvdata(pdev, hdmi); + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); } +static void dw_hdmi_rockchip_shutdown(struct platform_device *pdev) +{ + struct rockchip_hdmi *hdmi = dev_get_drvdata(&pdev->dev); + + if (!hdmi) + return; + + if (hdmi->is_hdmi_qp) { + cancel_delayed_work(&hdmi->work); + flush_workqueue(hdmi->workqueue); + dw_hdmi_qp_suspend(hdmi->dev, hdmi->hdmi_qp); + } else { + dw_hdmi_suspend(hdmi->hdmi); + } + pm_runtime_put_sync(&pdev->dev); +} + static void dw_hdmi_rockchip_remove(struct platform_device *pdev) { + struct rockchip_hdmi *hdmi = dev_get_drvdata(&pdev->dev); + component_del(&pdev->dev, &dw_hdmi_rockchip_ops); + pm_runtime_disable(&pdev->dev); + + if (hdmi->is_hdmi_qp) + destroy_workqueue(hdmi->workqueue); +} + +static int __maybe_unused dw_hdmi_rockchip_suspend(struct device *dev) +{ + struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + + if (hdmi->is_hdmi_qp) + dw_hdmi_qp_suspend(dev, hdmi->hdmi_qp); + else + dw_hdmi_suspend(hdmi->hdmi); + + pm_runtime_put_sync(dev); + + return 0; } static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev) { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); + u32 val; - dw_hdmi_resume(hdmi->hdmi); + if (hdmi->is_hdmi_qp) { + if (!hdmi->id) { + val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); + + val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, + RK3588_HDMI0_GRANT_SEL); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); + } else { + val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); + + val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); + + val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, + RK3588_HDMI1_GRANT_SEL); + regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); + } + + dw_hdmi_qp_resume(dev, hdmi->hdmi_qp); + drm_helper_hpd_irq_event(hdmi->drm_dev); + } else { + dw_hdmi_resume(hdmi->hdmi); + } + pm_runtime_get_sync(dev); return 0; } static const struct dev_pm_ops dw_hdmi_rockchip_pm = { - SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume) + SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_rockchip_suspend, + dw_hdmi_rockchip_resume) }; struct platform_driver dw_hdmi_rockchip_pltfm_driver = { .probe = dw_hdmi_rockchip_probe, .remove_new = dw_hdmi_rockchip_remove, + .shutdown = dw_hdmi_rockchip_shutdown, .driver = { .name = "dwhdmi-rockchip", .pm = &dw_hdmi_rockchip_pm, diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index 6a46baa0737c..ac4e418c1c4e 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -6,12 +6,14 @@ #ifndef __DW_HDMI__ #define __DW_HDMI__ +#include #include struct drm_display_info; struct drm_display_mode; struct drm_encoder; struct dw_hdmi; +struct dw_hdmi_qp; struct platform_device; /** @@ -92,6 +94,13 @@ enum dw_hdmi_phy_type { DW_HDMI_PHY_VENDOR_PHY = 0xfe, }; +struct dw_hdmi_audio_tmds_n { + unsigned long tmds; + unsigned int n_32k; + unsigned int n_44k1; + unsigned int n_48k; +}; + struct dw_hdmi_mpll_config { unsigned long mpixelclock; struct { @@ -112,6 +121,15 @@ struct dw_hdmi_phy_config { u16 vlev_ctr; /* voltage level control */ }; +struct dw_hdmi_link_config { + bool dsc_mode; + bool frl_mode; + int frl_lanes; + int rate_per_lane; + int hcactive; + u8 pps_payload[128]; +}; + struct dw_hdmi_phy_ops { int (*init)(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *display, @@ -123,14 +141,52 @@ struct dw_hdmi_phy_ops { void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); }; +struct dw_hdmi_qp_phy_ops { + int (*init)(struct dw_hdmi_qp *hdmi, void *data, + struct drm_display_mode *mode); + void (*disable)(struct dw_hdmi_qp *hdmi, void *data); + enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, + void *data); + void (*update_hpd)(struct dw_hdmi_qp *hdmi, void *data, + bool force, bool disabled, bool rxsense); + void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data); + void (*set_mode)(struct dw_hdmi_qp *dw_hdmi, void *data, + u32 mode_mask, bool enable); +}; + +struct dw_hdmi_property_ops { + void (*attach_properties)(struct drm_connector *connector, + unsigned int color, int version, + void *data); + void (*destroy_properties)(struct drm_connector *connector, + void *data); + int (*set_property)(struct drm_connector *connector, + struct drm_connector_state *state, + struct drm_property *property, + u64 val, + void *data); + int (*get_property)(struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + u64 *val, + void *data); +}; + struct dw_hdmi_plat_data { struct regmap *regm; + //[CC:] not in dowstream unsigned int output_port; + unsigned long input_bus_format; unsigned long input_bus_encoding; + unsigned int max_tmdsclk; + int id; bool use_drm_infoframe; bool ycbcr_420_allowed; + bool unsupported_yuv_input; + bool unsupported_deep_color; + bool is_hdmi_qp; /* * Private data passed to all the .mode_valid() and .configure_phy() @@ -139,6 +195,7 @@ struct dw_hdmi_plat_data { void *priv_data; /* Platform-specific mode validation (optional). */ + //[CC:] downstream changed "struct dw_hdmi *hdmi" to "struct drm_connector *connector" enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *info, const struct drm_display_mode *mode); @@ -150,18 +207,50 @@ struct dw_hdmi_plat_data { /* Vendor PHY support */ const struct dw_hdmi_phy_ops *phy_ops; + const struct dw_hdmi_qp_phy_ops *qp_phy_ops; const char *phy_name; void *phy_data; unsigned int phy_force_vendor; + /* split mode */ + bool split_mode; + bool first_screen; + struct dw_hdmi_qp *left; + struct dw_hdmi_qp *right; + /* Synopsys PHY support */ const struct dw_hdmi_mpll_config *mpll_cfg; + const struct dw_hdmi_mpll_config *mpll_cfg_420; const struct dw_hdmi_curr_ctrl *cur_ctr; const struct dw_hdmi_phy_config *phy_config; int (*configure_phy)(struct dw_hdmi *hdmi, void *data, unsigned long mpixelclock); unsigned int disable_cec : 1; + + //[CC:] 7b29b5f29585 ("drm/rockchip: dw_hdmi: Support HDMI 2.0 YCbCr 4:2:0") + unsigned long (*get_input_bus_format)(void *data); + unsigned long (*get_output_bus_format)(void *data); + unsigned long (*get_enc_in_encoding)(void *data); + unsigned long (*get_enc_out_encoding)(void *data); + + unsigned long (*get_quant_range)(void *data); + struct drm_property *(*get_hdr_property)(void *data); + struct drm_property_blob *(*get_hdr_blob)(void *data); + bool (*get_color_changed)(void *data); + int (*get_yuv422_format)(struct drm_connector *connector, + struct edid *edid); + int (*get_edid_dsc_info)(void *data, struct edid *edid); + int (*get_next_hdr_data)(void *data, struct edid *edid, + struct drm_connector *connector); + struct dw_hdmi_link_config *(*get_link_cfg)(void *data); + void (*set_grf_cfg)(void *data); + void (*convert_to_split_mode)(struct drm_display_mode *mode); + void (*convert_to_origin_mode)(struct drm_display_mode *mode); + + /* Vendor Property support */ + const struct dw_hdmi_property_ops *property_ops; + struct drm_connector *connector; }; struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, @@ -172,6 +261,7 @@ struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, const struct dw_hdmi_plat_data *plat_data); +void dw_hdmi_suspend(struct dw_hdmi *hdmi); void dw_hdmi_resume(struct dw_hdmi *hdmi); void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); @@ -205,6 +295,17 @@ enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense); void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); +void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi); +void dw_hdmi_set_output_type(struct dw_hdmi *hdmi, u64 val); +bool dw_hdmi_get_output_whether_hdmi(struct dw_hdmi *hdmi); +int dw_hdmi_get_output_type_cap(struct dw_hdmi *hdmi); + +void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi); +struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, + struct drm_encoder *encoder, + struct dw_hdmi_plat_data *plat_data); +void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi); +void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi); bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi); -- Armbian